Workload-driven selective hardening of control state elements in modern microprocessors

Mihalis Maniatakos, Yiorgos Makris

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present a method for selective hardening of control state elements against soft errors in modern microprocessors. In order to effectively allocate resources, our method seeks to rank the control state elements based on their susceptibility, taking into account the high degree of architectural masking inherent in modern microprocessors. The novelty of our method lies in the way this ranking is computed. Unlike methods that compute the architectural vulnerability of registers based on high-level simulations on performance models, our method operates at the Register Transfer (RT-) Level and is, therefore, more accurate. In contrast to previous RT-Level methods, however, it does not rely on extensive transient fault injection campaigns and lengthy executions of workloads to completion, which may make such analysis prohibitive. Instead, it monitors the behavior of key global microprocessor signals in response to a progressive stuckat fault injection method during partial workload execution. Experimentation with the Scheduler module of an Alpha-like microprocessor corroborates that our method generates a near-optimal ranking, yet is several orders of magnitude faster.

Original languageEnglish (US)
Title of host publicationProceedings - 28th IEEE VLSI Test Symposium, VTS10
Pages159-164
Number of pages6
DOIs
StatePublished - Jun 29 2010
Event28th IEEE VLSI Test Symposium, VTS10 - Santa Cruz, CA, United States
Duration: Apr 19 2010Apr 22 2010

Other

Other28th IEEE VLSI Test Symposium, VTS10
CountryUnited States
CitySanta Cruz, CA
Period4/19/104/22/10

Fingerprint

Hardening
Microprocessor chips

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

Maniatakos, M., & Makris, Y. (2010). Workload-driven selective hardening of control state elements in modern microprocessors. In Proceedings - 28th IEEE VLSI Test Symposium, VTS10 (pp. 159-164). [5469589] https://doi.org/10.1109/VTS.2010.5469589

Workload-driven selective hardening of control state elements in modern microprocessors. / Maniatakos, Mihalis; Makris, Yiorgos.

Proceedings - 28th IEEE VLSI Test Symposium, VTS10. 2010. p. 159-164 5469589.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Maniatakos, M & Makris, Y 2010, Workload-driven selective hardening of control state elements in modern microprocessors. in Proceedings - 28th IEEE VLSI Test Symposium, VTS10., 5469589, pp. 159-164, 28th IEEE VLSI Test Symposium, VTS10, Santa Cruz, CA, United States, 4/19/10. https://doi.org/10.1109/VTS.2010.5469589
Maniatakos M, Makris Y. Workload-driven selective hardening of control state elements in modern microprocessors. In Proceedings - 28th IEEE VLSI Test Symposium, VTS10. 2010. p. 159-164. 5469589 https://doi.org/10.1109/VTS.2010.5469589
Maniatakos, Mihalis ; Makris, Yiorgos. / Workload-driven selective hardening of control state elements in modern microprocessors. Proceedings - 28th IEEE VLSI Test Symposium, VTS10. 2010. pp. 159-164
@inproceedings{2ffff97116fc44d591a8c926df4c0440,
title = "Workload-driven selective hardening of control state elements in modern microprocessors",
abstract = "We present a method for selective hardening of control state elements against soft errors in modern microprocessors. In order to effectively allocate resources, our method seeks to rank the control state elements based on their susceptibility, taking into account the high degree of architectural masking inherent in modern microprocessors. The novelty of our method lies in the way this ranking is computed. Unlike methods that compute the architectural vulnerability of registers based on high-level simulations on performance models, our method operates at the Register Transfer (RT-) Level and is, therefore, more accurate. In contrast to previous RT-Level methods, however, it does not rely on extensive transient fault injection campaigns and lengthy executions of workloads to completion, which may make such analysis prohibitive. Instead, it monitors the behavior of key global microprocessor signals in response to a progressive stuckat fault injection method during partial workload execution. Experimentation with the Scheduler module of an Alpha-like microprocessor corroborates that our method generates a near-optimal ranking, yet is several orders of magnitude faster.",
author = "Mihalis Maniatakos and Yiorgos Makris",
year = "2010",
month = "6",
day = "29",
doi = "10.1109/VTS.2010.5469589",
language = "English (US)",
isbn = "9781424466481",
pages = "159--164",
booktitle = "Proceedings - 28th IEEE VLSI Test Symposium, VTS10",

}

TY - GEN

T1 - Workload-driven selective hardening of control state elements in modern microprocessors

AU - Maniatakos, Mihalis

AU - Makris, Yiorgos

PY - 2010/6/29

Y1 - 2010/6/29

N2 - We present a method for selective hardening of control state elements against soft errors in modern microprocessors. In order to effectively allocate resources, our method seeks to rank the control state elements based on their susceptibility, taking into account the high degree of architectural masking inherent in modern microprocessors. The novelty of our method lies in the way this ranking is computed. Unlike methods that compute the architectural vulnerability of registers based on high-level simulations on performance models, our method operates at the Register Transfer (RT-) Level and is, therefore, more accurate. In contrast to previous RT-Level methods, however, it does not rely on extensive transient fault injection campaigns and lengthy executions of workloads to completion, which may make such analysis prohibitive. Instead, it monitors the behavior of key global microprocessor signals in response to a progressive stuckat fault injection method during partial workload execution. Experimentation with the Scheduler module of an Alpha-like microprocessor corroborates that our method generates a near-optimal ranking, yet is several orders of magnitude faster.

AB - We present a method for selective hardening of control state elements against soft errors in modern microprocessors. In order to effectively allocate resources, our method seeks to rank the control state elements based on their susceptibility, taking into account the high degree of architectural masking inherent in modern microprocessors. The novelty of our method lies in the way this ranking is computed. Unlike methods that compute the architectural vulnerability of registers based on high-level simulations on performance models, our method operates at the Register Transfer (RT-) Level and is, therefore, more accurate. In contrast to previous RT-Level methods, however, it does not rely on extensive transient fault injection campaigns and lengthy executions of workloads to completion, which may make such analysis prohibitive. Instead, it monitors the behavior of key global microprocessor signals in response to a progressive stuckat fault injection method during partial workload execution. Experimentation with the Scheduler module of an Alpha-like microprocessor corroborates that our method generates a near-optimal ranking, yet is several orders of magnitude faster.

UR - http://www.scopus.com/inward/record.url?scp=77953905463&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77953905463&partnerID=8YFLogxK

U2 - 10.1109/VTS.2010.5469589

DO - 10.1109/VTS.2010.5469589

M3 - Conference contribution

AN - SCOPUS:77953905463

SN - 9781424466481

SP - 159

EP - 164

BT - Proceedings - 28th IEEE VLSI Test Symposium, VTS10

ER -