Wireless powering of mm-scale fully-on-chip neural interfaces

Jiwoong Park, Chul Kim, Abraham Akinin, Sohmyung Ha, Gert Cauwenberghs, Patrick P. Mercier

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    This paper presents guidelines for the design and optimization of on-chip coils used for wirelessly-powered mm-scale neural implants. Since available real estate is limited, on-chip coil design involves managing difficult trade-offs between the number of turns, trace width and spacing, proximity to other active circuits and metalization, quality factor, matching network performance/size, and load impedance conditions, all towards achieving high power transfer efficiency. To illustrate the design optimization procedure, a 3 × 3 mm2 on-chip coil is designed, and measurement results reveal a 3.82 % power transfer efficiency for a 1.6 kΩ load that mimics a 100 μW neural interface.

    Original languageEnglish (US)
    Title of host publication2017 IEEE Biomedical Circuits and Systems Conference, BioCAS 2017 - Proceedings
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages1-4
    Number of pages4
    Volume2018-January
    ISBN (Electronic)9781509058037
    DOIs
    StatePublished - Mar 23 2018
    Event2017 IEEE Biomedical Circuits and Systems Conference, BioCAS 2017 - Torino, Italy
    Duration: Oct 19 2017Oct 21 2017

    Other

    Other2017 IEEE Biomedical Circuits and Systems Conference, BioCAS 2017
    CountryItaly
    CityTorino
    Period10/19/1710/21/17

    Fingerprint

    coils
    chips
    Network performance
    design optimization
    Networks (circuits)
    proximity
    Q factors
    spacing
    impedance
    optimization
    Design optimization

    ASJC Scopus subject areas

    • Biomedical Engineering
    • Electrical and Electronic Engineering
    • Instrumentation

    Cite this

    Park, J., Kim, C., Akinin, A., Ha, S., Cauwenberghs, G., & Mercier, P. P. (2018). Wireless powering of mm-scale fully-on-chip neural interfaces. In 2017 IEEE Biomedical Circuits and Systems Conference, BioCAS 2017 - Proceedings (Vol. 2018-January, pp. 1-4). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/BIOCAS.2017.8325186

    Wireless powering of mm-scale fully-on-chip neural interfaces. / Park, Jiwoong; Kim, Chul; Akinin, Abraham; Ha, Sohmyung; Cauwenberghs, Gert; Mercier, Patrick P.

    2017 IEEE Biomedical Circuits and Systems Conference, BioCAS 2017 - Proceedings. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-4.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Park, J, Kim, C, Akinin, A, Ha, S, Cauwenberghs, G & Mercier, PP 2018, Wireless powering of mm-scale fully-on-chip neural interfaces. in 2017 IEEE Biomedical Circuits and Systems Conference, BioCAS 2017 - Proceedings. vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 2017 IEEE Biomedical Circuits and Systems Conference, BioCAS 2017, Torino, Italy, 10/19/17. https://doi.org/10.1109/BIOCAS.2017.8325186
    Park J, Kim C, Akinin A, Ha S, Cauwenberghs G, Mercier PP. Wireless powering of mm-scale fully-on-chip neural interfaces. In 2017 IEEE Biomedical Circuits and Systems Conference, BioCAS 2017 - Proceedings. Vol. 2018-January. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-4 https://doi.org/10.1109/BIOCAS.2017.8325186
    Park, Jiwoong ; Kim, Chul ; Akinin, Abraham ; Ha, Sohmyung ; Cauwenberghs, Gert ; Mercier, Patrick P. / Wireless powering of mm-scale fully-on-chip neural interfaces. 2017 IEEE Biomedical Circuits and Systems Conference, BioCAS 2017 - Proceedings. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. pp. 1-4
    @inproceedings{f6d17bea76e34ba3803fef80d48d143b,
    title = "Wireless powering of mm-scale fully-on-chip neural interfaces",
    abstract = "This paper presents guidelines for the design and optimization of on-chip coils used for wirelessly-powered mm-scale neural implants. Since available real estate is limited, on-chip coil design involves managing difficult trade-offs between the number of turns, trace width and spacing, proximity to other active circuits and metalization, quality factor, matching network performance/size, and load impedance conditions, all towards achieving high power transfer efficiency. To illustrate the design optimization procedure, a 3 × 3 mm2 on-chip coil is designed, and measurement results reveal a 3.82 {\%} power transfer efficiency for a 1.6 kΩ load that mimics a 100 μW neural interface.",
    author = "Jiwoong Park and Chul Kim and Abraham Akinin and Sohmyung Ha and Gert Cauwenberghs and Mercier, {Patrick P.}",
    year = "2018",
    month = "3",
    day = "23",
    doi = "10.1109/BIOCAS.2017.8325186",
    language = "English (US)",
    volume = "2018-January",
    pages = "1--4",
    booktitle = "2017 IEEE Biomedical Circuits and Systems Conference, BioCAS 2017 - Proceedings",
    publisher = "Institute of Electrical and Electronics Engineers Inc.",

    }

    TY - GEN

    T1 - Wireless powering of mm-scale fully-on-chip neural interfaces

    AU - Park, Jiwoong

    AU - Kim, Chul

    AU - Akinin, Abraham

    AU - Ha, Sohmyung

    AU - Cauwenberghs, Gert

    AU - Mercier, Patrick P.

    PY - 2018/3/23

    Y1 - 2018/3/23

    N2 - This paper presents guidelines for the design and optimization of on-chip coils used for wirelessly-powered mm-scale neural implants. Since available real estate is limited, on-chip coil design involves managing difficult trade-offs between the number of turns, trace width and spacing, proximity to other active circuits and metalization, quality factor, matching network performance/size, and load impedance conditions, all towards achieving high power transfer efficiency. To illustrate the design optimization procedure, a 3 × 3 mm2 on-chip coil is designed, and measurement results reveal a 3.82 % power transfer efficiency for a 1.6 kΩ load that mimics a 100 μW neural interface.

    AB - This paper presents guidelines for the design and optimization of on-chip coils used for wirelessly-powered mm-scale neural implants. Since available real estate is limited, on-chip coil design involves managing difficult trade-offs between the number of turns, trace width and spacing, proximity to other active circuits and metalization, quality factor, matching network performance/size, and load impedance conditions, all towards achieving high power transfer efficiency. To illustrate the design optimization procedure, a 3 × 3 mm2 on-chip coil is designed, and measurement results reveal a 3.82 % power transfer efficiency for a 1.6 kΩ load that mimics a 100 μW neural interface.

    UR - http://www.scopus.com/inward/record.url?scp=85050020116&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=85050020116&partnerID=8YFLogxK

    U2 - 10.1109/BIOCAS.2017.8325186

    DO - 10.1109/BIOCAS.2017.8325186

    M3 - Conference contribution

    VL - 2018-January

    SP - 1

    EP - 4

    BT - 2017 IEEE Biomedical Circuits and Systems Conference, BioCAS 2017 - Proceedings

    PB - Institute of Electrical and Electronics Engineers Inc.

    ER -