Voltage-controlled topological-spin switch for ultra-low-energy computation

Shaloo Rakheja, Michael E. Flatté, Andrew D. Kent

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we present the functionality and model the performance of a new spin-based logic device called the voltage-controlled topological-spin switch (vTOPSS). This device stores information in the magnetization of a thin magnetic insulator (MI) layer, which has ultra-fast dynamics and low-energy dissipation due to its small damping factor. To control the magnetization of the MI, a voltage signal is applied to a proximal topological insulator (TI) layer, which has a high charge-to-spin conversion efficiency at room temperature. The information in the MI layer is read using a magnetic tunnel junction (MTJ) voltage divider with sub-100 mV read voltages. Since its input/output state variables are in the voltage domain, the vTOPSS device does not require any transduction circuitry to be integrated with the CMOS technology. Device optimization shows that the vTOPSS device can operate with sub-25 aJ energy dissipation and < 30 nW power in on-state, these values are much lower than those reported in contemporary spin-based devices. Results confirm that the dominant component of energy dissipation is due to the TI leakage, which can be reduced by suppressing the surface and bulk charge conduction in the TI. Unlike CMOS devices, energy dissipation of the VTOPSS device is proportional to its switching delay. To simultaneously achieve low latency and energy dissipation in vTOPSS, a TI material with a large spin Hall conductivity and negligible charge conductivity is preferred. Interconnect burden on the performance of the vTOPSS device is minimal, which opens up the possibility of using highly resistive nanowires as potential interconnects for this technology.

Original languageEnglish (US)
Title of host publicationSpintronics XI
EditorsJean-Eric Wegrowe, Henri-Jean Drouhin, Manijeh Razeghi, Henri Jaffres
PublisherSPIE
Volume10732
ISBN (Electronic)9781510620353
DOIs
StatePublished - Jan 1 2018
EventSpintronics XI - San Diego, United States
Duration: Aug 19 2018Aug 23 2018

Other

OtherSpintronics XI
CountryUnited States
CitySan Diego
Period8/19/188/23/18

Fingerprint

Insulator
Switch
switches
Voltage
Switches
Energy Dissipation
insulators
Electric potential
electric potential
Energy dissipation
Energy
energy dissipation
energy
Charge
Interconnect
Magnetization
Conductivity
CMOS
Voltage dividers
Logic devices

Keywords

  • Beyond-CMOS computing
  • magnetic insulator
  • performance modeling
  • topological spintronics

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Computer Science Applications
  • Applied Mathematics
  • Electrical and Electronic Engineering

Cite this

Rakheja, S., Flatté, M. E., & Kent, A. D. (2018). Voltage-controlled topological-spin switch for ultra-low-energy computation. In J-E. Wegrowe, H-J. Drouhin, M. Razeghi, & H. Jaffres (Eds.), Spintronics XI (Vol. 10732). [1073238] SPIE. https://doi.org/10.1117/12.2323125

Voltage-controlled topological-spin switch for ultra-low-energy computation. / Rakheja, Shaloo; Flatté, Michael E.; Kent, Andrew D.

Spintronics XI. ed. / Jean-Eric Wegrowe; Henri-Jean Drouhin; Manijeh Razeghi; Henri Jaffres. Vol. 10732 SPIE, 2018. 1073238.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rakheja, S, Flatté, ME & Kent, AD 2018, Voltage-controlled topological-spin switch for ultra-low-energy computation. in J-E Wegrowe, H-J Drouhin, M Razeghi & H Jaffres (eds), Spintronics XI. vol. 10732, 1073238, SPIE, Spintronics XI, San Diego, United States, 8/19/18. https://doi.org/10.1117/12.2323125
Rakheja S, Flatté ME, Kent AD. Voltage-controlled topological-spin switch for ultra-low-energy computation. In Wegrowe J-E, Drouhin H-J, Razeghi M, Jaffres H, editors, Spintronics XI. Vol. 10732. SPIE. 2018. 1073238 https://doi.org/10.1117/12.2323125
Rakheja, Shaloo ; Flatté, Michael E. ; Kent, Andrew D. / Voltage-controlled topological-spin switch for ultra-low-energy computation. Spintronics XI. editor / Jean-Eric Wegrowe ; Henri-Jean Drouhin ; Manijeh Razeghi ; Henri Jaffres. Vol. 10732 SPIE, 2018.
@inproceedings{09e956d8ee6e4980a31ab1b929c18939,
title = "Voltage-controlled topological-spin switch for ultra-low-energy computation",
abstract = "In this paper, we present the functionality and model the performance of a new spin-based logic device called the voltage-controlled topological-spin switch (vTOPSS). This device stores information in the magnetization of a thin magnetic insulator (MI) layer, which has ultra-fast dynamics and low-energy dissipation due to its small damping factor. To control the magnetization of the MI, a voltage signal is applied to a proximal topological insulator (TI) layer, which has a high charge-to-spin conversion efficiency at room temperature. The information in the MI layer is read using a magnetic tunnel junction (MTJ) voltage divider with sub-100 mV read voltages. Since its input/output state variables are in the voltage domain, the vTOPSS device does not require any transduction circuitry to be integrated with the CMOS technology. Device optimization shows that the vTOPSS device can operate with sub-25 aJ energy dissipation and < 30 nW power in on-state, these values are much lower than those reported in contemporary spin-based devices. Results confirm that the dominant component of energy dissipation is due to the TI leakage, which can be reduced by suppressing the surface and bulk charge conduction in the TI. Unlike CMOS devices, energy dissipation of the VTOPSS device is proportional to its switching delay. To simultaneously achieve low latency and energy dissipation in vTOPSS, a TI material with a large spin Hall conductivity and negligible charge conductivity is preferred. Interconnect burden on the performance of the vTOPSS device is minimal, which opens up the possibility of using highly resistive nanowires as potential interconnects for this technology.",
keywords = "Beyond-CMOS computing, magnetic insulator, performance modeling, topological spintronics",
author = "Shaloo Rakheja and Flatt{\'e}, {Michael E.} and Kent, {Andrew D.}",
year = "2018",
month = "1",
day = "1",
doi = "10.1117/12.2323125",
language = "English (US)",
volume = "10732",
editor = "Jean-Eric Wegrowe and Henri-Jean Drouhin and Manijeh Razeghi and Henri Jaffres",
booktitle = "Spintronics XI",
publisher = "SPIE",

}

TY - GEN

T1 - Voltage-controlled topological-spin switch for ultra-low-energy computation

AU - Rakheja, Shaloo

AU - Flatté, Michael E.

AU - Kent, Andrew D.

PY - 2018/1/1

Y1 - 2018/1/1

N2 - In this paper, we present the functionality and model the performance of a new spin-based logic device called the voltage-controlled topological-spin switch (vTOPSS). This device stores information in the magnetization of a thin magnetic insulator (MI) layer, which has ultra-fast dynamics and low-energy dissipation due to its small damping factor. To control the magnetization of the MI, a voltage signal is applied to a proximal topological insulator (TI) layer, which has a high charge-to-spin conversion efficiency at room temperature. The information in the MI layer is read using a magnetic tunnel junction (MTJ) voltage divider with sub-100 mV read voltages. Since its input/output state variables are in the voltage domain, the vTOPSS device does not require any transduction circuitry to be integrated with the CMOS technology. Device optimization shows that the vTOPSS device can operate with sub-25 aJ energy dissipation and < 30 nW power in on-state, these values are much lower than those reported in contemporary spin-based devices. Results confirm that the dominant component of energy dissipation is due to the TI leakage, which can be reduced by suppressing the surface and bulk charge conduction in the TI. Unlike CMOS devices, energy dissipation of the VTOPSS device is proportional to its switching delay. To simultaneously achieve low latency and energy dissipation in vTOPSS, a TI material with a large spin Hall conductivity and negligible charge conductivity is preferred. Interconnect burden on the performance of the vTOPSS device is minimal, which opens up the possibility of using highly resistive nanowires as potential interconnects for this technology.

AB - In this paper, we present the functionality and model the performance of a new spin-based logic device called the voltage-controlled topological-spin switch (vTOPSS). This device stores information in the magnetization of a thin magnetic insulator (MI) layer, which has ultra-fast dynamics and low-energy dissipation due to its small damping factor. To control the magnetization of the MI, a voltage signal is applied to a proximal topological insulator (TI) layer, which has a high charge-to-spin conversion efficiency at room temperature. The information in the MI layer is read using a magnetic tunnel junction (MTJ) voltage divider with sub-100 mV read voltages. Since its input/output state variables are in the voltage domain, the vTOPSS device does not require any transduction circuitry to be integrated with the CMOS technology. Device optimization shows that the vTOPSS device can operate with sub-25 aJ energy dissipation and < 30 nW power in on-state, these values are much lower than those reported in contemporary spin-based devices. Results confirm that the dominant component of energy dissipation is due to the TI leakage, which can be reduced by suppressing the surface and bulk charge conduction in the TI. Unlike CMOS devices, energy dissipation of the VTOPSS device is proportional to its switching delay. To simultaneously achieve low latency and energy dissipation in vTOPSS, a TI material with a large spin Hall conductivity and negligible charge conductivity is preferred. Interconnect burden on the performance of the vTOPSS device is minimal, which opens up the possibility of using highly resistive nanowires as potential interconnects for this technology.

KW - Beyond-CMOS computing

KW - magnetic insulator

KW - performance modeling

KW - topological spintronics

UR - http://www.scopus.com/inward/record.url?scp=85055519843&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85055519843&partnerID=8YFLogxK

U2 - 10.1117/12.2323125

DO - 10.1117/12.2323125

M3 - Conference contribution

VL - 10732

BT - Spintronics XI

A2 - Wegrowe, Jean-Eric

A2 - Drouhin, Henri-Jean

A2 - Razeghi, Manijeh

A2 - Jaffres, Henri

PB - SPIE

ER -