Vertically-addressed test structures (VATS) for 3D IC variability and stress measurements

Conor O'Sullivan, Peter M. Levine, Siddharth Garg

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We propose a new test array architecture - vertically-addressed test structures (VATS) - to experimentally characterize the within-tier and tier-to-tier process variations and through-silicon via (TSV) induced stress in 3D integrated circuits (ICs). The proposed VATS architecture utilizes the benefits of 3D integration to simultaneously provide high density, low I/O pin utilization, and high fidelity. A test chip featuring eight VATS arrays (>15,000 active devices) has been designed and fabricated in a two-tier, 130-nm 3D IC technology. Simulation results highlight the advantages of the proposed VATS architecture compared to conventional 2D test arrays.We also propose a radial filtering scheme to discriminate between process variations and the impact of TSV-induced stress in 3D ICs.

Original languageEnglish (US)
Title of host publicationProceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013
Pages97-103
Number of pages7
DOIs
StatePublished - 2013
Event14th International Symposium on Quality Electronic Design, ISQED 2013 - Santa Clara, CA, United States
Duration: Mar 4 2013Mar 6 2013

Other

Other14th International Symposium on Quality Electronic Design, ISQED 2013
CountryUnited States
CitySanta Clara, CA
Period3/4/133/6/13

Fingerprint

Stress measurement
Silicon
Three dimensional integrated circuits

Keywords

  • 3D integrated circuit
  • test structures
  • variability

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

O'Sullivan, C., Levine, P. M., & Garg, S. (2013). Vertically-addressed test structures (VATS) for 3D IC variability and stress measurements. In Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013 (pp. 97-103). [6523596] https://doi.org/10.1109/ISQED.2013.6523596

Vertically-addressed test structures (VATS) for 3D IC variability and stress measurements. / O'Sullivan, Conor; Levine, Peter M.; Garg, Siddharth.

Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013. 2013. p. 97-103 6523596.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

O'Sullivan, C, Levine, PM & Garg, S 2013, Vertically-addressed test structures (VATS) for 3D IC variability and stress measurements. in Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013., 6523596, pp. 97-103, 14th International Symposium on Quality Electronic Design, ISQED 2013, Santa Clara, CA, United States, 3/4/13. https://doi.org/10.1109/ISQED.2013.6523596
O'Sullivan C, Levine PM, Garg S. Vertically-addressed test structures (VATS) for 3D IC variability and stress measurements. In Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013. 2013. p. 97-103. 6523596 https://doi.org/10.1109/ISQED.2013.6523596
O'Sullivan, Conor ; Levine, Peter M. ; Garg, Siddharth. / Vertically-addressed test structures (VATS) for 3D IC variability and stress measurements. Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013. 2013. pp. 97-103
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