Vertical flash memory with protein-mediated assembly of nanocrystal floating gate

Joy Sarkar, Shan Tang, Davood Shahrjerdi, Sanjay K. Banerjee

Research output: Contribution to journalArticle

Abstract

The authors propose and demonstrate a vertical flash memory device incorporating protein-mediated ordering of nanocrystal floating gate to help circumvent density scaling and/or performance limitations of planar flash memory with continuous floating gate. The scalability of the vertical architecture can allow the theoretical maximum array density of 14 F2 (F: minimum lithographic pitch), thus circumventing the integration density limitations of planar flash transistor arrays. The nanocrystal floating gate renders reasonable retention, while the protein-mediated ordering of nanocrystals allows scalability and manufacturability. With tunneling program/erase, a memory window of 0.5 V, endurance > 105 cycles, and retention beyond 105 s is reported.

Original languageEnglish (US)
Article number103512
JournalApplied Physics Letters
Volume90
Issue number10
DOIs
StatePublished - 2007

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floating
flash
nanocrystals
assembly
proteins
endurance
transistors
scaling
cycles

ASJC Scopus subject areas

  • Physics and Astronomy (miscellaneous)

Cite this

Vertical flash memory with protein-mediated assembly of nanocrystal floating gate. / Sarkar, Joy; Tang, Shan; Shahrjerdi, Davood; Banerjee, Sanjay K.

In: Applied Physics Letters, Vol. 90, No. 10, 103512, 2007.

Research output: Contribution to journalArticle

@article{1bf02046c9db46fd824fb2b30386e510,
title = "Vertical flash memory with protein-mediated assembly of nanocrystal floating gate",
abstract = "The authors propose and demonstrate a vertical flash memory device incorporating protein-mediated ordering of nanocrystal floating gate to help circumvent density scaling and/or performance limitations of planar flash memory with continuous floating gate. The scalability of the vertical architecture can allow the theoretical maximum array density of 14 F2 (F: minimum lithographic pitch), thus circumventing the integration density limitations of planar flash transistor arrays. The nanocrystal floating gate renders reasonable retention, while the protein-mediated ordering of nanocrystals allows scalability and manufacturability. With tunneling program/erase, a memory window of 0.5 V, endurance > 105 cycles, and retention beyond 105 s is reported.",
author = "Joy Sarkar and Shan Tang and Davood Shahrjerdi and Banerjee, {Sanjay K.}",
year = "2007",
doi = "10.1063/1.2711528",
language = "English (US)",
volume = "90",
journal = "Applied Physics Letters",
issn = "0003-6951",
publisher = "American Institute of Physics Publising LLC",
number = "10",

}

TY - JOUR

T1 - Vertical flash memory with protein-mediated assembly of nanocrystal floating gate

AU - Sarkar, Joy

AU - Tang, Shan

AU - Shahrjerdi, Davood

AU - Banerjee, Sanjay K.

PY - 2007

Y1 - 2007

N2 - The authors propose and demonstrate a vertical flash memory device incorporating protein-mediated ordering of nanocrystal floating gate to help circumvent density scaling and/or performance limitations of planar flash memory with continuous floating gate. The scalability of the vertical architecture can allow the theoretical maximum array density of 14 F2 (F: minimum lithographic pitch), thus circumventing the integration density limitations of planar flash transistor arrays. The nanocrystal floating gate renders reasonable retention, while the protein-mediated ordering of nanocrystals allows scalability and manufacturability. With tunneling program/erase, a memory window of 0.5 V, endurance > 105 cycles, and retention beyond 105 s is reported.

AB - The authors propose and demonstrate a vertical flash memory device incorporating protein-mediated ordering of nanocrystal floating gate to help circumvent density scaling and/or performance limitations of planar flash memory with continuous floating gate. The scalability of the vertical architecture can allow the theoretical maximum array density of 14 F2 (F: minimum lithographic pitch), thus circumventing the integration density limitations of planar flash transistor arrays. The nanocrystal floating gate renders reasonable retention, while the protein-mediated ordering of nanocrystals allows scalability and manufacturability. With tunneling program/erase, a memory window of 0.5 V, endurance > 105 cycles, and retention beyond 105 s is reported.

UR - http://www.scopus.com/inward/record.url?scp=33947151655&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33947151655&partnerID=8YFLogxK

U2 - 10.1063/1.2711528

DO - 10.1063/1.2711528

M3 - Article

VL - 90

JO - Applied Physics Letters

JF - Applied Physics Letters

SN - 0003-6951

IS - 10

M1 - 103512

ER -