Transport of novel state variables

Shaloo Rakheja, Azad Naeemi

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

In this chapter, a framework is developed for comparison of different post-CMOS interconnect technologies using physical models of transport mechanisms for these novel interconnects. In the first part of the chapter, an overview of CMOS interconnects is provided with an emphasis on the impact of scaling on the performance and energy dissipation of local (<100 gate pitches) interconnects. The second part of the chapter deals with the delay modeling of novel interconnects. The upper bound on the performance of novel interconnects is benchmarked against their conventional CMOS counterparts. A set of guidelines is derived at the device and circuit level for post-CMOS technologies.

Original languageEnglish (US)
Title of host publicationGraphene Nanoelectronics
Subtitle of host publicationFrom Materials to Circuits
PublisherSpringer US
Pages113-136
Number of pages24
Volume9781461405481
ISBN (Electronic)9781461405481
ISBN (Print)1461405475, 9781461405474
DOIs
StatePublished - Nov 1 2013

    Fingerprint

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Rakheja, S., & Naeemi, A. (2013). Transport of novel state variables. In Graphene Nanoelectronics: From Materials to Circuits (Vol. 9781461405481, pp. 113-136). Springer US. https://doi.org/10.1007/978-1-4614-0548-1_5