Abstract
Networks-on-Chips (NoCs) are meeting the growing inter-tile communication needs of multicore chips. However, achieving system scalability by utilizing hundreds of cores on-chip requires high performance, yet energy-efficient on-chip interconnects. As electrical interconnects are marred by high energy-to-bandwidth costs, threatening multicore scalability, on-chip nanophotonics, which offer high throughput, yet energy-efficient communication, are an alternative attractive solution. In this paper we consider silicon nanophotonic components that are embedded completely within the silica (SiO2) substrate as opposed to prior-art that utilizes die on-surface silicon nanophotonics. As nanophotonic components now reside in the silica substrate's subsurface, a greater portion of a chip's real estate can be utilized by cores and routers, while non-obstructive interconnect geometries offering higher network throughput can be implemented. First, we show using detailed simulations based on commercial tools that such silicon-in-silica (SiS) structures are feasible, and then demonstrate our proof of concept by utilizing a hybrid SiS-based photonic mesh-diagonal links topology that provides both higher effective throughput and throughput-to-power ratio versus prior-art.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - 2015 9th International Workshop on Interconnection Network Architectures |
| Subtitle of host publication | On-Chip, Multi-Chip, INA-OCMC 2015 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 1-4 |
| Number of pages | 4 |
| ISBN (Electronic) | 9781479918706 |
| DOIs | |
| State | Published - Jan 1 2015 |
| Event | 2015 9th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, INA-OCMC 2015 - Amsterdam, Netherlands Duration: Jan 19 2015 → … |
Other
| Other | 2015 9th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, INA-OCMC 2015 |
|---|---|
| Country | Netherlands |
| City | Amsterdam |
| Period | 1/19/15 → … |
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Keywords
- Nanophotonics
- Networks-on-Chips
- Photonic Interconnects
- Silicon-in-Silica
ASJC Scopus subject areas
- Computer Networks and Communications
- Software
Cite this
Towards high-performance and power-efficient optical NoCs using silicon-in-silica photonic components. / Kakoulli, Elena; Soteriou, Vassos Soteriou; Koutsides, Charalambos; Kalli, Kyriacos.
Proceedings - 2015 9th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, INA-OCMC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 1-4 7051994.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Towards high-performance and power-efficient optical NoCs using silicon-in-silica photonic components
AU - Kakoulli, Elena
AU - Soteriou, Vassos Soteriou
AU - Koutsides, Charalambos
AU - Kalli, Kyriacos
PY - 2015/1/1
Y1 - 2015/1/1
N2 - Networks-on-Chips (NoCs) are meeting the growing inter-tile communication needs of multicore chips. However, achieving system scalability by utilizing hundreds of cores on-chip requires high performance, yet energy-efficient on-chip interconnects. As electrical interconnects are marred by high energy-to-bandwidth costs, threatening multicore scalability, on-chip nanophotonics, which offer high throughput, yet energy-efficient communication, are an alternative attractive solution. In this paper we consider silicon nanophotonic components that are embedded completely within the silica (SiO2) substrate as opposed to prior-art that utilizes die on-surface silicon nanophotonics. As nanophotonic components now reside in the silica substrate's subsurface, a greater portion of a chip's real estate can be utilized by cores and routers, while non-obstructive interconnect geometries offering higher network throughput can be implemented. First, we show using detailed simulations based on commercial tools that such silicon-in-silica (SiS) structures are feasible, and then demonstrate our proof of concept by utilizing a hybrid SiS-based photonic mesh-diagonal links topology that provides both higher effective throughput and throughput-to-power ratio versus prior-art.
AB - Networks-on-Chips (NoCs) are meeting the growing inter-tile communication needs of multicore chips. However, achieving system scalability by utilizing hundreds of cores on-chip requires high performance, yet energy-efficient on-chip interconnects. As electrical interconnects are marred by high energy-to-bandwidth costs, threatening multicore scalability, on-chip nanophotonics, which offer high throughput, yet energy-efficient communication, are an alternative attractive solution. In this paper we consider silicon nanophotonic components that are embedded completely within the silica (SiO2) substrate as opposed to prior-art that utilizes die on-surface silicon nanophotonics. As nanophotonic components now reside in the silica substrate's subsurface, a greater portion of a chip's real estate can be utilized by cores and routers, while non-obstructive interconnect geometries offering higher network throughput can be implemented. First, we show using detailed simulations based on commercial tools that such silicon-in-silica (SiS) structures are feasible, and then demonstrate our proof of concept by utilizing a hybrid SiS-based photonic mesh-diagonal links topology that provides both higher effective throughput and throughput-to-power ratio versus prior-art.
KW - Nanophotonics
KW - Networks-on-Chips
KW - Photonic Interconnects
KW - Silicon-in-Silica
UR - http://www.scopus.com/inward/record.url?scp=84934297043&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84934297043&partnerID=8YFLogxK
U2 - 10.1109/INA-OCMC.2015.12
DO - 10.1109/INA-OCMC.2015.12
M3 - Conference contribution
AN - SCOPUS:84934297043
SP - 1
EP - 4
BT - Proceedings - 2015 9th International Workshop on Interconnection Network Architectures
PB - Institute of Electrical and Electronics Engineers Inc.
ER -