Time-constrained scheduling during high-level synthesis of fault-secure VLSI digital signal processors

Ramesh Karri, Alex Orailoglu

Research output: Contribution to journalArticle

Abstract

Advances in VLSI technology are making it feasible to pack millions of transistors on a single chip, A consequent increase in the number of on-chip faults as well as the growing importance of quality-metrics such as reliability & fault-tolerance are making on-chip fault-tolerance mandatory. Onchip realization of a computation is fault-secure if an observable error in the computation is detected. Components used in lifecritical systems should be secured against all faults. While faultsecurity can be realized by duplicating the computation on disjoint hardware and voting on the result(s), such straightforward strategies entail appreciable hardware overhead. This paper presents computer-aided behavioral synthesis of fault-secure microarchitectures which require less than proportional increase in hardware. The strategy selects intermediate computations for additional voting. The resulting class of fault-secure microarchitectures supplants the enormous hardware requirements of naive faultsecure strategies with enhanced hardware utilization afforded by securing the intermediate computations. Experimental results show that fault-security can be implemented at a less than proportional increase in hardware overhead.

Original languageEnglish (US)
Pages (from-to)404-412
Number of pages9
JournalIEEE Transactions on Reliability
Volume45
Issue number3
DOIs
StatePublished - 1996

Fingerprint

Digital signal processors
Scheduling
Hardware
Fault tolerance
Computer hardware
Transistors
High level synthesis

Keywords

  • Fault-security
  • Faulttolerance
  • Vlsi architecture
  • Vlsi synthesis

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Computer Graphics and Computer-Aided Design
  • Software
  • Safety, Risk, Reliability and Quality

Cite this

Time-constrained scheduling during high-level synthesis of fault-secure VLSI digital signal processors. / Karri, Ramesh; Orailoglu, Alex.

In: IEEE Transactions on Reliability, Vol. 45, No. 3, 1996, p. 404-412.

Research output: Contribution to journalArticle

@article{9fefc286e7e2423c8d3743ebd9a3e67e,
title = "Time-constrained scheduling during high-level synthesis of fault-secure VLSI digital signal processors",
abstract = "Advances in VLSI technology are making it feasible to pack millions of transistors on a single chip, A consequent increase in the number of on-chip faults as well as the growing importance of quality-metrics such as reliability & fault-tolerance are making on-chip fault-tolerance mandatory. Onchip realization of a computation is fault-secure if an observable error in the computation is detected. Components used in lifecritical systems should be secured against all faults. While faultsecurity can be realized by duplicating the computation on disjoint hardware and voting on the result(s), such straightforward strategies entail appreciable hardware overhead. This paper presents computer-aided behavioral synthesis of fault-secure microarchitectures which require less than proportional increase in hardware. The strategy selects intermediate computations for additional voting. The resulting class of fault-secure microarchitectures supplants the enormous hardware requirements of naive faultsecure strategies with enhanced hardware utilization afforded by securing the intermediate computations. Experimental results show that fault-security can be implemented at a less than proportional increase in hardware overhead.",
keywords = "Fault-security, Faulttolerance, Vlsi architecture, Vlsi synthesis",
author = "Ramesh Karri and Alex Orailoglu",
year = "1996",
doi = "10.1109/24.536993",
language = "English (US)",
volume = "45",
pages = "404--412",
journal = "IEEE Transactions on Reliability",
issn = "0018-9529",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "3",

}

TY - JOUR

T1 - Time-constrained scheduling during high-level synthesis of fault-secure VLSI digital signal processors

AU - Karri, Ramesh

AU - Orailoglu, Alex

PY - 1996

Y1 - 1996

N2 - Advances in VLSI technology are making it feasible to pack millions of transistors on a single chip, A consequent increase in the number of on-chip faults as well as the growing importance of quality-metrics such as reliability & fault-tolerance are making on-chip fault-tolerance mandatory. Onchip realization of a computation is fault-secure if an observable error in the computation is detected. Components used in lifecritical systems should be secured against all faults. While faultsecurity can be realized by duplicating the computation on disjoint hardware and voting on the result(s), such straightforward strategies entail appreciable hardware overhead. This paper presents computer-aided behavioral synthesis of fault-secure microarchitectures which require less than proportional increase in hardware. The strategy selects intermediate computations for additional voting. The resulting class of fault-secure microarchitectures supplants the enormous hardware requirements of naive faultsecure strategies with enhanced hardware utilization afforded by securing the intermediate computations. Experimental results show that fault-security can be implemented at a less than proportional increase in hardware overhead.

AB - Advances in VLSI technology are making it feasible to pack millions of transistors on a single chip, A consequent increase in the number of on-chip faults as well as the growing importance of quality-metrics such as reliability & fault-tolerance are making on-chip fault-tolerance mandatory. Onchip realization of a computation is fault-secure if an observable error in the computation is detected. Components used in lifecritical systems should be secured against all faults. While faultsecurity can be realized by duplicating the computation on disjoint hardware and voting on the result(s), such straightforward strategies entail appreciable hardware overhead. This paper presents computer-aided behavioral synthesis of fault-secure microarchitectures which require less than proportional increase in hardware. The strategy selects intermediate computations for additional voting. The resulting class of fault-secure microarchitectures supplants the enormous hardware requirements of naive faultsecure strategies with enhanced hardware utilization afforded by securing the intermediate computations. Experimental results show that fault-security can be implemented at a less than proportional increase in hardware overhead.

KW - Fault-security

KW - Faulttolerance

KW - Vlsi architecture

KW - Vlsi synthesis

UR - http://www.scopus.com/inward/record.url?scp=0030245132&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030245132&partnerID=8YFLogxK

U2 - 10.1109/24.536993

DO - 10.1109/24.536993

M3 - Article

VL - 45

SP - 404

EP - 412

JO - IEEE Transactions on Reliability

JF - IEEE Transactions on Reliability

SN - 0018-9529

IS - 3

ER -