The ATM layer chip: An ASIC for B-ISDN applications

Cesar A. Johnston, H. Jonathan Chao

Research output: Contribution to journalArticle

Abstract

The authors describe the architecture of an experimental research prototype application specific integrated circuit (ASIC) designed to serve as a generic building block of the future broadband integrated services digital network (B-ISDN). The chip performs common asynchronous transfer mode (ATM) layer functions such as cell assembly and cell disassembly. A new media access control (MAC) protocol developed for a broadband customer premises network is also integrated in the chip. The chip interfaces to the B-ISDN through a synchronous optical network (SONET) synchronous transmission signal-3c (STS-3c) framer chip. The ATM layer chip has been designed using 1.2 μm CMOS technology with a die area of 5.4 × 5.4 mm2 and approximately 27,000 transistors. Experimental results are described. At the user network interface, the chip can be used to implement broadband terminal adaptors and the network termination. At the broadband local exchange, the chip can be used in the implementation of ATM statistical multiplexers, ATM switch port controllers, etc.

Original languageEnglish (US)
Pages (from-to)741-750
Number of pages10
JournalIEEE Journal on Selected Areas in Communications
Volume9
Issue number5
DOIs
StatePublished - Jun 1991

Fingerprint

Voice/data communication systems
Asynchronous transfer mode
Application specific integrated circuits
Medium access control
Fiber optic networks
Interfaces (computer)
Transistors
Switches
Network protocols
Controllers

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

The ATM layer chip : An ASIC for B-ISDN applications. / Johnston, Cesar A.; Chao, H. Jonathan.

In: IEEE Journal on Selected Areas in Communications, Vol. 9, No. 5, 06.1991, p. 741-750.

Research output: Contribution to journalArticle

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