Abstract
Toggling of scan cells during the shift of consecutive complementary values reflects into excessive switching activity in the combinational logic under test unnecessarily. Elevated levels of power dissipation during test ensue as a result, endangering the reliability of the chip. The test power problem may be alleviated via a proper specification of don't care bits to create transition-less runs of bit values. However, in order to reduce Test Data Volume (TDV), these don't care bits are typically exploited to encode patterns through the on-chip decompressor. Furthermore, this approach would not address scan-out and/or capture power. In this paper, we propose a DfT-based approach for reducing test power in any scan architecture. The proposed on-chip mechanism enables the alignment of transition-wise costly stimulus/response bits in scan slices, absorbing these transitions and reducing power. The proposed solution is test set independent and reduces power without resorting to x-filling, enabling orthogonal x-filling techniques to be applied in conjunction. Experimental results justify the efficacy of the proposed method in attaining test power reductions.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 573-584 |
| Number of pages | 12 |
| Journal | Journal of Low Power Electronics |
| Volume | 7 |
| Issue number | 4 |
| DOIs | |
| State | Published - Dec 1 2011 |
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Keywords
- Low-Power Test
- Scan-Based Test
- Stimulus and Response Bits Alignment
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
Test power reduction via deterministic alignment of stimulus and response bits. / Almukhaizim, Sobeeh; AlQuraishi, Eman; Sinanoglu, Ozgur.
In: Journal of Low Power Electronics, Vol. 7, No. 4, 01.12.2011, p. 573-584.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Test power reduction via deterministic alignment of stimulus and response bits
AU - Almukhaizim, Sobeeh
AU - AlQuraishi, Eman
AU - Sinanoglu, Ozgur
PY - 2011/12/1
Y1 - 2011/12/1
N2 - Toggling of scan cells during the shift of consecutive complementary values reflects into excessive switching activity in the combinational logic under test unnecessarily. Elevated levels of power dissipation during test ensue as a result, endangering the reliability of the chip. The test power problem may be alleviated via a proper specification of don't care bits to create transition-less runs of bit values. However, in order to reduce Test Data Volume (TDV), these don't care bits are typically exploited to encode patterns through the on-chip decompressor. Furthermore, this approach would not address scan-out and/or capture power. In this paper, we propose a DfT-based approach for reducing test power in any scan architecture. The proposed on-chip mechanism enables the alignment of transition-wise costly stimulus/response bits in scan slices, absorbing these transitions and reducing power. The proposed solution is test set independent and reduces power without resorting to x-filling, enabling orthogonal x-filling techniques to be applied in conjunction. Experimental results justify the efficacy of the proposed method in attaining test power reductions.
AB - Toggling of scan cells during the shift of consecutive complementary values reflects into excessive switching activity in the combinational logic under test unnecessarily. Elevated levels of power dissipation during test ensue as a result, endangering the reliability of the chip. The test power problem may be alleviated via a proper specification of don't care bits to create transition-less runs of bit values. However, in order to reduce Test Data Volume (TDV), these don't care bits are typically exploited to encode patterns through the on-chip decompressor. Furthermore, this approach would not address scan-out and/or capture power. In this paper, we propose a DfT-based approach for reducing test power in any scan architecture. The proposed on-chip mechanism enables the alignment of transition-wise costly stimulus/response bits in scan slices, absorbing these transitions and reducing power. The proposed solution is test set independent and reduces power without resorting to x-filling, enabling orthogonal x-filling techniques to be applied in conjunction. Experimental results justify the efficacy of the proposed method in attaining test power reductions.
KW - Low-Power Test
KW - Scan-Based Test
KW - Stimulus and Response Bits Alignment
UR - http://www.scopus.com/inward/record.url?scp=84857287859&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84857287859&partnerID=8YFLogxK
U2 - 10.1166/jolpe.2011.1152
DO - 10.1166/jolpe.2011.1152
M3 - Article
AN - SCOPUS:84857287859
VL - 7
SP - 573
EP - 584
JO - Journal of Low Power Electronics
JF - Journal of Low Power Electronics
SN - 1546-1998
IS - 4
ER -