Test power reduction via deterministic alignment of stimulus and response bits

Sobeeh Almukhaizim, Eman AlQuraishi, Ozgur Sinanoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Toggling of scan cells during the shift of consecutive complementary values reflects into excessive switching activity in the combinational logic under test unnecessarily. Elevated levels of power dissipation during test ensue as a result, endangering the reliability of the chip. The test power problem may be alleviated via a proper specification of don't care bits to create transition-less runs of bit values. However, in order to reduce Test Data Volume (TDV), these don't care bits are typically exploited to encode patterns through the on-chip decompressor. Furthermore, this approach would not address scan-out and/or capture power. In this paper, we propose a DfT-based approach for reducing test power in any scan architecture. The proposed on-chip mechanism enables the alignment of transition-wise costly stimulus/response bits in scan slices, absorbing these transitions and reducing power. The proposed solution is test set independent and reduces power without resorting to x-filling, enabling orthogonal x-filling techniques to be applied in conjunction. Experimental results justify the efficacy of the proposed method in attaining test power reductions.

Original languageEnglish (US)
Title of host publicationLATW 2011 - 12th IEEE Latin-American Test Workshop
DOIs
StatePublished - Sep 15 2011
Event12th IEEE Latin-American Test Workshop, LATW 2011 - Porto de Galinhas, Brazil
Duration: Mar 27 2011Mar 30 2011

Other

Other12th IEEE Latin-American Test Workshop, LATW 2011
CountryBrazil
CityPorto de Galinhas
Period3/27/113/30/11

Fingerprint

Energy dissipation
Specifications

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Almukhaizim, S., AlQuraishi, E., & Sinanoglu, O. (2011). Test power reduction via deterministic alignment of stimulus and response bits. In LATW 2011 - 12th IEEE Latin-American Test Workshop [5985911] https://doi.org/10.1109/LATW.2011.5985911

Test power reduction via deterministic alignment of stimulus and response bits. / Almukhaizim, Sobeeh; AlQuraishi, Eman; Sinanoglu, Ozgur.

LATW 2011 - 12th IEEE Latin-American Test Workshop. 2011. 5985911.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Almukhaizim, S, AlQuraishi, E & Sinanoglu, O 2011, Test power reduction via deterministic alignment of stimulus and response bits. in LATW 2011 - 12th IEEE Latin-American Test Workshop., 5985911, 12th IEEE Latin-American Test Workshop, LATW 2011, Porto de Galinhas, Brazil, 3/27/11. https://doi.org/10.1109/LATW.2011.5985911
Almukhaizim S, AlQuraishi E, Sinanoglu O. Test power reduction via deterministic alignment of stimulus and response bits. In LATW 2011 - 12th IEEE Latin-American Test Workshop. 2011. 5985911 https://doi.org/10.1109/LATW.2011.5985911
Almukhaizim, Sobeeh ; AlQuraishi, Eman ; Sinanoglu, Ozgur. / Test power reduction via deterministic alignment of stimulus and response bits. LATW 2011 - 12th IEEE Latin-American Test Workshop. 2011.
@inproceedings{d6cbcdf6abf5443ab2ed2946b20e8a27,
title = "Test power reduction via deterministic alignment of stimulus and response bits",
abstract = "Toggling of scan cells during the shift of consecutive complementary values reflects into excessive switching activity in the combinational logic under test unnecessarily. Elevated levels of power dissipation during test ensue as a result, endangering the reliability of the chip. The test power problem may be alleviated via a proper specification of don't care bits to create transition-less runs of bit values. However, in order to reduce Test Data Volume (TDV), these don't care bits are typically exploited to encode patterns through the on-chip decompressor. Furthermore, this approach would not address scan-out and/or capture power. In this paper, we propose a DfT-based approach for reducing test power in any scan architecture. The proposed on-chip mechanism enables the alignment of transition-wise costly stimulus/response bits in scan slices, absorbing these transitions and reducing power. The proposed solution is test set independent and reduces power without resorting to x-filling, enabling orthogonal x-filling techniques to be applied in conjunction. Experimental results justify the efficacy of the proposed method in attaining test power reductions.",
author = "Sobeeh Almukhaizim and Eman AlQuraishi and Ozgur Sinanoglu",
year = "2011",
month = "9",
day = "15",
doi = "10.1109/LATW.2011.5985911",
language = "English (US)",
isbn = "9781457714900",
booktitle = "LATW 2011 - 12th IEEE Latin-American Test Workshop",

}

TY - GEN

T1 - Test power reduction via deterministic alignment of stimulus and response bits

AU - Almukhaizim, Sobeeh

AU - AlQuraishi, Eman

AU - Sinanoglu, Ozgur

PY - 2011/9/15

Y1 - 2011/9/15

N2 - Toggling of scan cells during the shift of consecutive complementary values reflects into excessive switching activity in the combinational logic under test unnecessarily. Elevated levels of power dissipation during test ensue as a result, endangering the reliability of the chip. The test power problem may be alleviated via a proper specification of don't care bits to create transition-less runs of bit values. However, in order to reduce Test Data Volume (TDV), these don't care bits are typically exploited to encode patterns through the on-chip decompressor. Furthermore, this approach would not address scan-out and/or capture power. In this paper, we propose a DfT-based approach for reducing test power in any scan architecture. The proposed on-chip mechanism enables the alignment of transition-wise costly stimulus/response bits in scan slices, absorbing these transitions and reducing power. The proposed solution is test set independent and reduces power without resorting to x-filling, enabling orthogonal x-filling techniques to be applied in conjunction. Experimental results justify the efficacy of the proposed method in attaining test power reductions.

AB - Toggling of scan cells during the shift of consecutive complementary values reflects into excessive switching activity in the combinational logic under test unnecessarily. Elevated levels of power dissipation during test ensue as a result, endangering the reliability of the chip. The test power problem may be alleviated via a proper specification of don't care bits to create transition-less runs of bit values. However, in order to reduce Test Data Volume (TDV), these don't care bits are typically exploited to encode patterns through the on-chip decompressor. Furthermore, this approach would not address scan-out and/or capture power. In this paper, we propose a DfT-based approach for reducing test power in any scan architecture. The proposed on-chip mechanism enables the alignment of transition-wise costly stimulus/response bits in scan slices, absorbing these transitions and reducing power. The proposed solution is test set independent and reduces power without resorting to x-filling, enabling orthogonal x-filling techniques to be applied in conjunction. Experimental results justify the efficacy of the proposed method in attaining test power reductions.

UR - http://www.scopus.com/inward/record.url?scp=80052621167&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80052621167&partnerID=8YFLogxK

U2 - 10.1109/LATW.2011.5985911

DO - 10.1109/LATW.2011.5985911

M3 - Conference contribution

SN - 9781457714900

BT - LATW 2011 - 12th IEEE Latin-American Test Workshop

ER -