Test power reduction through minimization of scan chain transitions

Ozgur Sinanoglu, I. Bayraktaroglu, A. Orailoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result infrequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. No performance degradation ensues as scan chain modifications have no impact on functional execution. A computationally efficient scheme is proposed to identify, the location and type of the logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.

Original languageEnglish (US)
Title of host publicationProceedings - 20th IEEE VLSI Test Symposium, VTS 2002
PublisherIEEE Computer Society
Pages166-171
Number of pages6
Volume2002-January
ISBN (Electronic)0769515703
DOIs
StatePublished - Jan 1 2002
Event20th IEEE VLSI Test Symposium, VTS 2002 - Monterey, United States
Duration: Apr 28 2002May 2 2002

Other

Other20th IEEE VLSI Test Symposium, VTS 2002
CountryUnited States
CityMonterey
Period4/28/025/2/02

Fingerprint

Switching circuits
Degradation

Keywords

  • Automatic test pattern generation
  • Circuit testing
  • Costs
  • Degradation
  • Frequency
  • Logic testing
  • Power dissipation
  • Switching circuits
  • System testing
  • System-on-a-chip

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

Sinanoglu, O., Bayraktaroglu, I., & Orailoglu, A. (2002). Test power reduction through minimization of scan chain transitions. In Proceedings - 20th IEEE VLSI Test Symposium, VTS 2002 (Vol. 2002-January, pp. 166-171). [1011129] IEEE Computer Society. https://doi.org/10.1109/VTS.2002.1011129

Test power reduction through minimization of scan chain transitions. / Sinanoglu, Ozgur; Bayraktaroglu, I.; Orailoglu, A.

Proceedings - 20th IEEE VLSI Test Symposium, VTS 2002. Vol. 2002-January IEEE Computer Society, 2002. p. 166-171 1011129.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sinanoglu, O, Bayraktaroglu, I & Orailoglu, A 2002, Test power reduction through minimization of scan chain transitions. in Proceedings - 20th IEEE VLSI Test Symposium, VTS 2002. vol. 2002-January, 1011129, IEEE Computer Society, pp. 166-171, 20th IEEE VLSI Test Symposium, VTS 2002, Monterey, United States, 4/28/02. https://doi.org/10.1109/VTS.2002.1011129
Sinanoglu O, Bayraktaroglu I, Orailoglu A. Test power reduction through minimization of scan chain transitions. In Proceedings - 20th IEEE VLSI Test Symposium, VTS 2002. Vol. 2002-January. IEEE Computer Society. 2002. p. 166-171. 1011129 https://doi.org/10.1109/VTS.2002.1011129
Sinanoglu, Ozgur ; Bayraktaroglu, I. ; Orailoglu, A. / Test power reduction through minimization of scan chain transitions. Proceedings - 20th IEEE VLSI Test Symposium, VTS 2002. Vol. 2002-January IEEE Computer Society, 2002. pp. 166-171
@inproceedings{bb836a2fdf9d416cabcc7cc453aae822,
title = "Test power reduction through minimization of scan chain transitions",
abstract = "Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result infrequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. No performance degradation ensues as scan chain modifications have no impact on functional execution. A computationally efficient scheme is proposed to identify, the location and type of the logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.",
keywords = "Automatic test pattern generation, Circuit testing, Costs, Degradation, Frequency, Logic testing, Power dissipation, Switching circuits, System testing, System-on-a-chip",
author = "Ozgur Sinanoglu and I. Bayraktaroglu and A. Orailoglu",
year = "2002",
month = "1",
day = "1",
doi = "10.1109/VTS.2002.1011129",
language = "English (US)",
volume = "2002-January",
pages = "166--171",
booktitle = "Proceedings - 20th IEEE VLSI Test Symposium, VTS 2002",
publisher = "IEEE Computer Society",

}

TY - GEN

T1 - Test power reduction through minimization of scan chain transitions

AU - Sinanoglu, Ozgur

AU - Bayraktaroglu, I.

AU - Orailoglu, A.

PY - 2002/1/1

Y1 - 2002/1/1

N2 - Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result infrequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. No performance degradation ensues as scan chain modifications have no impact on functional execution. A computationally efficient scheme is proposed to identify, the location and type of the logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.

AB - Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result infrequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. No performance degradation ensues as scan chain modifications have no impact on functional execution. A computationally efficient scheme is proposed to identify, the location and type of the logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.

KW - Automatic test pattern generation

KW - Circuit testing

KW - Costs

KW - Degradation

KW - Frequency

KW - Logic testing

KW - Power dissipation

KW - Switching circuits

KW - System testing

KW - System-on-a-chip

UR - http://www.scopus.com/inward/record.url?scp=84948443429&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84948443429&partnerID=8YFLogxK

U2 - 10.1109/VTS.2002.1011129

DO - 10.1109/VTS.2002.1011129

M3 - Conference contribution

AN - SCOPUS:84948443429

VL - 2002-January

SP - 166

EP - 171

BT - Proceedings - 20th IEEE VLSI Test Symposium, VTS 2002

PB - IEEE Computer Society

ER -