Abstract
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result infrequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. No performance degradation ensues as scan chain modifications have no impact on functional execution. A computationally efficient scheme is proposed to identify, the location and type of the logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.
Original language | English (US) |
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Title of host publication | Proceedings - 20th IEEE VLSI Test Symposium, VTS 2002 |
Publisher | IEEE Computer Society |
Pages | 166-171 |
Number of pages | 6 |
Volume | 2002-January |
ISBN (Electronic) | 0769515703 |
DOIs | |
State | Published - Jan 1 2002 |
Event | 20th IEEE VLSI Test Symposium, VTS 2002 - Monterey, United States Duration: Apr 28 2002 → May 2 2002 |
Other
Other | 20th IEEE VLSI Test Symposium, VTS 2002 |
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Country | United States |
City | Monterey |
Period | 4/28/02 → 5/2/02 |
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Keywords
- Automatic test pattern generation
- Circuit testing
- Costs
- Degradation
- Frequency
- Logic testing
- Power dissipation
- Switching circuits
- System testing
- System-on-a-chip
ASJC Scopus subject areas
- Computer Science Applications
- Electrical and Electronic Engineering
Cite this
Test power reduction through minimization of scan chain transitions. / Sinanoglu, Ozgur; Bayraktaroglu, I.; Orailoglu, A.
Proceedings - 20th IEEE VLSI Test Symposium, VTS 2002. Vol. 2002-January IEEE Computer Society, 2002. p. 166-171 1011129.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Test power reduction through minimization of scan chain transitions
AU - Sinanoglu, Ozgur
AU - Bayraktaroglu, I.
AU - Orailoglu, A.
PY - 2002/1/1
Y1 - 2002/1/1
N2 - Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result infrequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. No performance degradation ensues as scan chain modifications have no impact on functional execution. A computationally efficient scheme is proposed to identify, the location and type of the logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.
AB - Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result infrequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. No performance degradation ensues as scan chain modifications have no impact on functional execution. A computationally efficient scheme is proposed to identify, the location and type of the logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.
KW - Automatic test pattern generation
KW - Circuit testing
KW - Costs
KW - Degradation
KW - Frequency
KW - Logic testing
KW - Power dissipation
KW - Switching circuits
KW - System testing
KW - System-on-a-chip
UR - http://www.scopus.com/inward/record.url?scp=84948443429&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84948443429&partnerID=8YFLogxK
U2 - 10.1109/VTS.2002.1011129
DO - 10.1109/VTS.2002.1011129
M3 - Conference contribution
AN - SCOPUS:84948443429
VL - 2002-January
SP - 166
EP - 171
BT - Proceedings - 20th IEEE VLSI Test Symposium, VTS 2002
PB - IEEE Computer Society
ER -