Test power reduction through minimization of scan chain transitions

Ozgur Sinanoglu, I. Bayraktaroglu, A. Orailoglu

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    Abstract

    Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result infrequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. No performance degradation ensues as scan chain modifications have no impact on functional execution. A computationally efficient scheme is proposed to identify, the location and type of the logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.

    Original languageEnglish (US)
    Title of host publicationProceedings - 20th IEEE VLSI Test Symposium, VTS 2002
    PublisherIEEE Computer Society
    Pages166-171
    Number of pages6
    Volume2002-January
    ISBN (Electronic)0769515703
    DOIs
    StatePublished - Jan 1 2002
    Event20th IEEE VLSI Test Symposium, VTS 2002 - Monterey, United States
    Duration: Apr 28 2002 → May 2 2002

    Other

    Other20th IEEE VLSI Test Symposium, VTS 2002
    CountryUnited States
    CityMonterey
    Period4/28/02 → 5/2/02

    Fingerprint

    Switching circuits
    Degradation

    Keywords

    • Automatic test pattern generation
    • Circuit testing
    • Costs
    • Degradation
    • Frequency
    • Logic testing
    • Power dissipation
    • Switching circuits
    • System testing
    • System-on-a-chip

    ASJC Scopus subject areas

    • Computer Science Applications
    • Electrical and Electronic Engineering

    Cite this

    Sinanoglu, O., Bayraktaroglu, I., & Orailoglu, A. (2002). Test power reduction through minimization of scan chain transitions. In Proceedings - 20th IEEE VLSI Test Symposium, VTS 2002 (Vol. 2002-January, pp. 166-171). [1011129] IEEE Computer Society. https://doi.org/10.1109/VTS.2002.1011129

    Test power reduction through minimization of scan chain transitions. / Sinanoglu, Ozgur; Bayraktaroglu, I.; Orailoglu, A.

    Proceedings - 20th IEEE VLSI Test Symposium, VTS 2002. Vol. 2002-January IEEE Computer Society, 2002. p. 166-171 1011129.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    Sinanoglu, O, Bayraktaroglu, I & Orailoglu, A 2002, Test power reduction through minimization of scan chain transitions. in Proceedings - 20th IEEE VLSI Test Symposium, VTS 2002. vol. 2002-January, 1011129, IEEE Computer Society, pp. 166-171, 20th IEEE VLSI Test Symposium, VTS 2002, Monterey, United States, 4/28/02. https://doi.org/10.1109/VTS.2002.1011129
    Sinanoglu O, Bayraktaroglu I, Orailoglu A. Test power reduction through minimization of scan chain transitions. In Proceedings - 20th IEEE VLSI Test Symposium, VTS 2002. Vol. 2002-January. IEEE Computer Society. 2002. p. 166-171. 1011129 https://doi.org/10.1109/VTS.2002.1011129
    Sinanoglu, Ozgur ; Bayraktaroglu, I. ; Orailoglu, A. / Test power reduction through minimization of scan chain transitions. Proceedings - 20th IEEE VLSI Test Symposium, VTS 2002. Vol. 2002-January IEEE Computer Society, 2002. pp. 166-171
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