Tagged probabilistic simulation based error probability estimation for better-than-worst case circuit design

Amr Tosson, Siddharth Garg, Mohab Anis

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Better than worst-case (BWC) design is an design emerging paradigm in which the conservative frequency guard-bands used in conventional designs are removed at the expense of introducing a a non-zero (but small) error probability. A fundamental challenge in the design of better-than-worst-case circuits is to devise scalable and accurate techniques for error-probability estimation-in this paper we present a new solution to address this challenge using the concept of tagged probabilistic simulations (TPS), which were first introduced in the context of dynamic power estimation. We show that TPS can, in comparison to the existing state-of-the-art, (a) provide consistent speed-up over error probability estimation using timing simulations; and (b) simultaneously provide estimates of both dynamic power dissipation and error probability. To illustrate the benefits of TPS based error probability estimation, we propose two power optimization techniques: a) a gate-level dual-VDD assignment tool b) a gate-sizing technique which optimize the cells used in a design for a certain error and power constraints.

Original languageEnglish (US)
Title of host publication2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings
PublisherIEEE Computer Society
Pages368-373
Number of pages6
ISBN (Print)9781479905249
DOIs
StatePublished - 2013
Event2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Istanbul, Turkey
Duration: Oct 7 2013Oct 9 2013

Other

Other2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013
CountryTurkey
CityIstanbul
Period10/7/1310/9/13

Fingerprint

Networks (circuits)
Energy dissipation
Error probability

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

Cite this

Tosson, A., Garg, S., & Anis, M. (2013). Tagged probabilistic simulation based error probability estimation for better-than-worst case circuit design. In 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings (pp. 368-373). [6673311] IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2013.6673311

Tagged probabilistic simulation based error probability estimation for better-than-worst case circuit design. / Tosson, Amr; Garg, Siddharth; Anis, Mohab.

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings. IEEE Computer Society, 2013. p. 368-373 6673311.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tosson, A, Garg, S & Anis, M 2013, Tagged probabilistic simulation based error probability estimation for better-than-worst case circuit design. in 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings., 6673311, IEEE Computer Society, pp. 368-373, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, 10/7/13. https://doi.org/10.1109/VLSI-SoC.2013.6673311
Tosson A, Garg S, Anis M. Tagged probabilistic simulation based error probability estimation for better-than-worst case circuit design. In 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings. IEEE Computer Society. 2013. p. 368-373. 6673311 https://doi.org/10.1109/VLSI-SoC.2013.6673311
Tosson, Amr ; Garg, Siddharth ; Anis, Mohab. / Tagged probabilistic simulation based error probability estimation for better-than-worst case circuit design. 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings. IEEE Computer Society, 2013. pp. 368-373
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