System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs

Siddharth Garg, Diana Marculescu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Manufacturing process variations are the primary cause of timing yield loss in aggressively scaled technologies. In this paper, we analyze the impact of process variations on the throughput (rate) characteristics of embedded systems comprised of multiple voltage-frequency islands (VFIs) represented as component graphs. We provide an efficient, yet accurate method to compute the throughput of an application in a probabilistic scenario and show that systems implemented with multiple VFIs are more likely to meet throughput constraints than their fully synchronous counterparts. The proposed framework allows designers to investigate the impact of architectural decisions such as the granularity of VFI partitioning on their designs, while determining the likelihood of a system meeting specified throughput constraints. An implementation of the proposed framework is accurate within 1.2% of Monte Carlo simulation while yielding speedups ranging from 78X-260X, for a set of synthetic benchmarks. Results on a real benchmark (MPEG-2 encoder) show that a nine clock domain implementation gives 100% yield for a throughput constraint for which a fully synchronous design only yields 25%. For the same throughput constraint, a three clock domain architecture yields 78%.

Original languageEnglish (US)
Title of host publicationProceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007
Pages403-408
Number of pages6
DOIs
StatePublished - 2007
Event2007 Design, Automation and Test in Europe Conference and Exhibition - Nice Acropolis, France
Duration: Apr 16 2007Apr 20 2007

Other

Other2007 Design, Automation and Test in Europe Conference and Exhibition
CountryFrance
CityNice Acropolis
Period4/16/074/20/07

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Throughput
Electric potential
Clocks
Embedded systems

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Garg, S., & Marculescu, D. (2007). System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs. In Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007 (pp. 403-408). [4211830] https://doi.org/10.1109/DATE.2007.364625

System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs. / Garg, Siddharth; Marculescu, Diana.

Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007. 2007. p. 403-408 4211830.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Garg, S & Marculescu, D 2007, System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs. in Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007., 4211830, pp. 403-408, 2007 Design, Automation and Test in Europe Conference and Exhibition, Nice Acropolis, France, 4/16/07. https://doi.org/10.1109/DATE.2007.364625
Garg S, Marculescu D. System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs. In Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007. 2007. p. 403-408. 4211830 https://doi.org/10.1109/DATE.2007.364625
Garg, Siddharth ; Marculescu, Diana. / System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs. Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007. 2007. pp. 403-408
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