System-level process variability analysis and mitigation for 3D MPSoCs

Siddharth Garg, Diana Marculescu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

While prior research has extensively evaluated the performance advantage of moving from a 2D to a 3D design style, the impact of process parameter variations on 3D designs has been largely ignored. In this paper, we attempt to bridge this gap by proposing a variability-aware design framework for fully-synchronous (FS) and multiple clock-domain (MCD) 3D systems. First, we develop analytical system-level models of the impact of process variations on the performance of FS 3D designs. The accuracy of the model is demonstrated by comparing against transistorlevel Monte Carlo simulations in SPICE - we observe a maximum error of only 0:7% (average 0:31% error) in the mean of the maximum critical path delay distribution. Second, to mitigate the impact of process variations on 3D designs, we propose a variability-aware 3D integration strategy for MCD 3D systems that maximizes the probability of the design meeting specified system performance constraints. The proposed optimization strategy is shown to significantly outperform FS and MCD 3D implementations that are conventionally assembled - for example, the MCD designs assembled with the proposed integration strategy provide, on average, 44% and 16:33% higher absolute yield than the FS and conventional MCD designs respectively, at the 50% yield point of the conventional MCD designs.

Original languageEnglish (US)
Title of host publicationProceedings - 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09
Pages604-609
Number of pages6
StatePublished - 2009
Event2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09 - Nice, France
Duration: Apr 20 2009Apr 24 2009

Other

Other2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09
CountryFrance
CityNice
Period4/20/094/24/09

Fingerprint

Clocks
SPICE

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Garg, S., & Marculescu, D. (2009). System-level process variability analysis and mitigation for 3D MPSoCs. In Proceedings - 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09 (pp. 604-609). [5090739]

System-level process variability analysis and mitigation for 3D MPSoCs. / Garg, Siddharth; Marculescu, Diana.

Proceedings - 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09. 2009. p. 604-609 5090739.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Garg, S & Marculescu, D 2009, System-level process variability analysis and mitigation for 3D MPSoCs. in Proceedings - 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09., 5090739, pp. 604-609, 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09, Nice, France, 4/20/09.
Garg S, Marculescu D. System-level process variability analysis and mitigation for 3D MPSoCs. In Proceedings - 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09. 2009. p. 604-609. 5090739
Garg, Siddharth ; Marculescu, Diana. / System-level process variability analysis and mitigation for 3D MPSoCs. Proceedings - 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09. 2009. pp. 604-609
@inproceedings{86df655e3565426fa5394d493b1ad47a,
title = "System-level process variability analysis and mitigation for 3D MPSoCs",
abstract = "While prior research has extensively evaluated the performance advantage of moving from a 2D to a 3D design style, the impact of process parameter variations on 3D designs has been largely ignored. In this paper, we attempt to bridge this gap by proposing a variability-aware design framework for fully-synchronous (FS) and multiple clock-domain (MCD) 3D systems. First, we develop analytical system-level models of the impact of process variations on the performance of FS 3D designs. The accuracy of the model is demonstrated by comparing against transistorlevel Monte Carlo simulations in SPICE - we observe a maximum error of only 0:7{\%} (average 0:31{\%} error) in the mean of the maximum critical path delay distribution. Second, to mitigate the impact of process variations on 3D designs, we propose a variability-aware 3D integration strategy for MCD 3D systems that maximizes the probability of the design meeting specified system performance constraints. The proposed optimization strategy is shown to significantly outperform FS and MCD 3D implementations that are conventionally assembled - for example, the MCD designs assembled with the proposed integration strategy provide, on average, 44{\%} and 16:33{\%} higher absolute yield than the FS and conventional MCD designs respectively, at the 50{\%} yield point of the conventional MCD designs.",
author = "Siddharth Garg and Diana Marculescu",
year = "2009",
language = "English (US)",
isbn = "9783981080155",
pages = "604--609",
booktitle = "Proceedings - 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09",

}

TY - GEN

T1 - System-level process variability analysis and mitigation for 3D MPSoCs

AU - Garg, Siddharth

AU - Marculescu, Diana

PY - 2009

Y1 - 2009

N2 - While prior research has extensively evaluated the performance advantage of moving from a 2D to a 3D design style, the impact of process parameter variations on 3D designs has been largely ignored. In this paper, we attempt to bridge this gap by proposing a variability-aware design framework for fully-synchronous (FS) and multiple clock-domain (MCD) 3D systems. First, we develop analytical system-level models of the impact of process variations on the performance of FS 3D designs. The accuracy of the model is demonstrated by comparing against transistorlevel Monte Carlo simulations in SPICE - we observe a maximum error of only 0:7% (average 0:31% error) in the mean of the maximum critical path delay distribution. Second, to mitigate the impact of process variations on 3D designs, we propose a variability-aware 3D integration strategy for MCD 3D systems that maximizes the probability of the design meeting specified system performance constraints. The proposed optimization strategy is shown to significantly outperform FS and MCD 3D implementations that are conventionally assembled - for example, the MCD designs assembled with the proposed integration strategy provide, on average, 44% and 16:33% higher absolute yield than the FS and conventional MCD designs respectively, at the 50% yield point of the conventional MCD designs.

AB - While prior research has extensively evaluated the performance advantage of moving from a 2D to a 3D design style, the impact of process parameter variations on 3D designs has been largely ignored. In this paper, we attempt to bridge this gap by proposing a variability-aware design framework for fully-synchronous (FS) and multiple clock-domain (MCD) 3D systems. First, we develop analytical system-level models of the impact of process variations on the performance of FS 3D designs. The accuracy of the model is demonstrated by comparing against transistorlevel Monte Carlo simulations in SPICE - we observe a maximum error of only 0:7% (average 0:31% error) in the mean of the maximum critical path delay distribution. Second, to mitigate the impact of process variations on 3D designs, we propose a variability-aware 3D integration strategy for MCD 3D systems that maximizes the probability of the design meeting specified system performance constraints. The proposed optimization strategy is shown to significantly outperform FS and MCD 3D implementations that are conventionally assembled - for example, the MCD designs assembled with the proposed integration strategy provide, on average, 44% and 16:33% higher absolute yield than the FS and conventional MCD designs respectively, at the 50% yield point of the conventional MCD designs.

UR - http://www.scopus.com/inward/record.url?scp=70350043905&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=70350043905&partnerID=8YFLogxK

M3 - Conference contribution

SN - 9783981080155

SP - 604

EP - 609

BT - Proceedings - 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09

ER -