System-level mitigation of WID leakage power variability using body-bias islands

Siddharth Garg, Diana Marculescu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Adaptive Body Biasing (ABB) is a popularly used technique to mitigate the increasing impact of manufacturing process variations on leakage power dissipation. The efficacy of the ABB technique can be improved by partitioning a design into a number of "body-bias islands," each with its individual body-bias voltage. In this paper, we propose a system-level leakage variability mitigation framework to partition a multiprocessor system into body-bias islands at the processing element (PE) granularity at design time, and to optimally assign body-bias voltages to each island post-fabrication. As opposed to prior gate- and circuit-level partitioning techniques that constrain the global clock frequency of the system, we allow each island to run at a different speed and constrain only the relevant system performance metrics - in our case the execution deadlines. Experimental results show the efficacy of the proposed framework in reducing the mean and standard deviation of leakage power dissipation compared to a baseline system without ABB. At the same time, the proposed techniques provide significant runtime improvements over a previously proposed Monte-Carlo based technique while providing similar reductions in leakage power dissipation.

Original languageEnglish (US)
Title of host publicationEmbedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008
Pages273-278
Number of pages6
DOIs
StatePublished - 2008
EventEmbedded Systems Week 2008 - 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008 - Atlanta, GA, United States
Duration: Oct 19 2008Oct 24 2008

Other

OtherEmbedded Systems Week 2008 - 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008
CountryUnited States
CityAtlanta, GA
Period10/19/0810/24/08

Fingerprint

Energy dissipation
Bias voltage
Adaptive systems
Clocks
Fabrication
Networks (circuits)
Processing

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

Cite this

Garg, S., & Marculescu, D. (2008). System-level mitigation of WID leakage power variability using body-bias islands. In Embedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008 (pp. 273-278) https://doi.org/10.1145/1450135.1450197

System-level mitigation of WID leakage power variability using body-bias islands. / Garg, Siddharth; Marculescu, Diana.

Embedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008. 2008. p. 273-278.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Garg, S & Marculescu, D 2008, System-level mitigation of WID leakage power variability using body-bias islands. in Embedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008. pp. 273-278, Embedded Systems Week 2008 - 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, United States, 10/19/08. https://doi.org/10.1145/1450135.1450197
Garg S, Marculescu D. System-level mitigation of WID leakage power variability using body-bias islands. In Embedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008. 2008. p. 273-278 https://doi.org/10.1145/1450135.1450197
Garg, Siddharth ; Marculescu, Diana. / System-level mitigation of WID leakage power variability using body-bias islands. Embedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008. 2008. pp. 273-278
@inproceedings{449355f3a9a241938af852dfa61a84f6,
title = "System-level mitigation of WID leakage power variability using body-bias islands",
abstract = "Adaptive Body Biasing (ABB) is a popularly used technique to mitigate the increasing impact of manufacturing process variations on leakage power dissipation. The efficacy of the ABB technique can be improved by partitioning a design into a number of {"}body-bias islands,{"} each with its individual body-bias voltage. In this paper, we propose a system-level leakage variability mitigation framework to partition a multiprocessor system into body-bias islands at the processing element (PE) granularity at design time, and to optimally assign body-bias voltages to each island post-fabrication. As opposed to prior gate- and circuit-level partitioning techniques that constrain the global clock frequency of the system, we allow each island to run at a different speed and constrain only the relevant system performance metrics - in our case the execution deadlines. Experimental results show the efficacy of the proposed framework in reducing the mean and standard deviation of leakage power dissipation compared to a baseline system without ABB. At the same time, the proposed techniques provide significant runtime improvements over a previously proposed Monte-Carlo based technique while providing similar reductions in leakage power dissipation.",
author = "Siddharth Garg and Diana Marculescu",
year = "2008",
doi = "10.1145/1450135.1450197",
language = "English (US)",
isbn = "9781605584706",
pages = "273--278",
booktitle = "Embedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008",

}

TY - GEN

T1 - System-level mitigation of WID leakage power variability using body-bias islands

AU - Garg, Siddharth

AU - Marculescu, Diana

PY - 2008

Y1 - 2008

N2 - Adaptive Body Biasing (ABB) is a popularly used technique to mitigate the increasing impact of manufacturing process variations on leakage power dissipation. The efficacy of the ABB technique can be improved by partitioning a design into a number of "body-bias islands," each with its individual body-bias voltage. In this paper, we propose a system-level leakage variability mitigation framework to partition a multiprocessor system into body-bias islands at the processing element (PE) granularity at design time, and to optimally assign body-bias voltages to each island post-fabrication. As opposed to prior gate- and circuit-level partitioning techniques that constrain the global clock frequency of the system, we allow each island to run at a different speed and constrain only the relevant system performance metrics - in our case the execution deadlines. Experimental results show the efficacy of the proposed framework in reducing the mean and standard deviation of leakage power dissipation compared to a baseline system without ABB. At the same time, the proposed techniques provide significant runtime improvements over a previously proposed Monte-Carlo based technique while providing similar reductions in leakage power dissipation.

AB - Adaptive Body Biasing (ABB) is a popularly used technique to mitigate the increasing impact of manufacturing process variations on leakage power dissipation. The efficacy of the ABB technique can be improved by partitioning a design into a number of "body-bias islands," each with its individual body-bias voltage. In this paper, we propose a system-level leakage variability mitigation framework to partition a multiprocessor system into body-bias islands at the processing element (PE) granularity at design time, and to optimally assign body-bias voltages to each island post-fabrication. As opposed to prior gate- and circuit-level partitioning techniques that constrain the global clock frequency of the system, we allow each island to run at a different speed and constrain only the relevant system performance metrics - in our case the execution deadlines. Experimental results show the efficacy of the proposed framework in reducing the mean and standard deviation of leakage power dissipation compared to a baseline system without ABB. At the same time, the proposed techniques provide significant runtime improvements over a previously proposed Monte-Carlo based technique while providing similar reductions in leakage power dissipation.

UR - http://www.scopus.com/inward/record.url?scp=63349103590&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=63349103590&partnerID=8YFLogxK

U2 - 10.1145/1450135.1450197

DO - 10.1145/1450135.1450197

M3 - Conference contribution

AN - SCOPUS:63349103590

SN - 9781605584706

SP - 273

EP - 278

BT - Embedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008

ER -