Statistical thermal evaluation and mitigation techniques for 3D chip-multiprocessors in the presence of process variations

Da Cheng Juan, Siddharth Garg, Diana Marculescu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Thermal issues have become critical roadblocks for achieving highly reliable three-dimensional (3D) integrated circuits. This paper performs both the evaluation and mitigation of the impact of leakage power variations on the temperature profile of 3D Chip-Multiprocessors (CMPs). Furthermore, this paper provides a learning-based model to predict the maximum temperature, based on which a simple, yet effective tier-stacking algorithm to mitigate the impact of variations on the temperature profile of 3D CMPs is proposed. Results show that (1) the proposed prediction model achieves more than 98% accuracy, (2) a 4-tier 3D implementation can be more than 40°C hotter than its 2D counterpart and (3) the proposed tier-stacking algorithm significantly improves the thermal yield from 44.4% to 81.1% for a 3D CMP.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011
Pages383-388
Number of pages6
StatePublished - 2011
Event14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011 - Grenoble, France
Duration: Mar 14 2011Mar 18 2011

Other

Other14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011
CountryFrance
CityGrenoble
Period3/14/113/18/11

Fingerprint

Temperature
Hot Temperature
Three dimensional integrated circuits

Keywords

  • 3D
  • chip-multiprocessor
  • leakage
  • process variation
  • regression
  • stack
  • statistical learning
  • thermal
  • yield

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Juan, D. C., Garg, S., & Marculescu, D. (2011). Statistical thermal evaluation and mitigation techniques for 3D chip-multiprocessors in the presence of process variations. In Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011 (pp. 383-388). [5763067]

Statistical thermal evaluation and mitigation techniques for 3D chip-multiprocessors in the presence of process variations. / Juan, Da Cheng; Garg, Siddharth; Marculescu, Diana.

Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011. 2011. p. 383-388 5763067.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Juan, DC, Garg, S & Marculescu, D 2011, Statistical thermal evaluation and mitigation techniques for 3D chip-multiprocessors in the presence of process variations. in Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011., 5763067, pp. 383-388, 14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011, Grenoble, France, 3/14/11.
Juan DC, Garg S, Marculescu D. Statistical thermal evaluation and mitigation techniques for 3D chip-multiprocessors in the presence of process variations. In Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011. 2011. p. 383-388. 5763067
Juan, Da Cheng ; Garg, Siddharth ; Marculescu, Diana. / Statistical thermal evaluation and mitigation techniques for 3D chip-multiprocessors in the presence of process variations. Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011. 2011. pp. 383-388
@inproceedings{d0af67be3f3d45ba9938e7b82b6fb3ea,
title = "Statistical thermal evaluation and mitigation techniques for 3D chip-multiprocessors in the presence of process variations",
abstract = "Thermal issues have become critical roadblocks for achieving highly reliable three-dimensional (3D) integrated circuits. This paper performs both the evaluation and mitigation of the impact of leakage power variations on the temperature profile of 3D Chip-Multiprocessors (CMPs). Furthermore, this paper provides a learning-based model to predict the maximum temperature, based on which a simple, yet effective tier-stacking algorithm to mitigate the impact of variations on the temperature profile of 3D CMPs is proposed. Results show that (1) the proposed prediction model achieves more than 98{\%} accuracy, (2) a 4-tier 3D implementation can be more than 40°C hotter than its 2D counterpart and (3) the proposed tier-stacking algorithm significantly improves the thermal yield from 44.4{\%} to 81.1{\%} for a 3D CMP.",
keywords = "3D, chip-multiprocessor, leakage, process variation, regression, stack, statistical learning, thermal, yield",
author = "Juan, {Da Cheng} and Siddharth Garg and Diana Marculescu",
year = "2011",
language = "English (US)",
isbn = "9783981080179",
pages = "383--388",
booktitle = "Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011",

}

TY - GEN

T1 - Statistical thermal evaluation and mitigation techniques for 3D chip-multiprocessors in the presence of process variations

AU - Juan, Da Cheng

AU - Garg, Siddharth

AU - Marculescu, Diana

PY - 2011

Y1 - 2011

N2 - Thermal issues have become critical roadblocks for achieving highly reliable three-dimensional (3D) integrated circuits. This paper performs both the evaluation and mitigation of the impact of leakage power variations on the temperature profile of 3D Chip-Multiprocessors (CMPs). Furthermore, this paper provides a learning-based model to predict the maximum temperature, based on which a simple, yet effective tier-stacking algorithm to mitigate the impact of variations on the temperature profile of 3D CMPs is proposed. Results show that (1) the proposed prediction model achieves more than 98% accuracy, (2) a 4-tier 3D implementation can be more than 40°C hotter than its 2D counterpart and (3) the proposed tier-stacking algorithm significantly improves the thermal yield from 44.4% to 81.1% for a 3D CMP.

AB - Thermal issues have become critical roadblocks for achieving highly reliable three-dimensional (3D) integrated circuits. This paper performs both the evaluation and mitigation of the impact of leakage power variations on the temperature profile of 3D Chip-Multiprocessors (CMPs). Furthermore, this paper provides a learning-based model to predict the maximum temperature, based on which a simple, yet effective tier-stacking algorithm to mitigate the impact of variations on the temperature profile of 3D CMPs is proposed. Results show that (1) the proposed prediction model achieves more than 98% accuracy, (2) a 4-tier 3D implementation can be more than 40°C hotter than its 2D counterpart and (3) the proposed tier-stacking algorithm significantly improves the thermal yield from 44.4% to 81.1% for a 3D CMP.

KW - 3D

KW - chip-multiprocessor

KW - leakage

KW - process variation

KW - regression

KW - stack

KW - statistical learning

KW - thermal

KW - yield

UR - http://www.scopus.com/inward/record.url?scp=79957579528&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79957579528&partnerID=8YFLogxK

M3 - Conference contribution

SN - 9783981080179

SP - 383

EP - 388

BT - Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011

ER -