Split manufacturing

Siddharth Garg, Jeyavijayan J V Rajendran

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

This chapter discusses split manufacturing, a promising hardware obfuscation technique that partitions a chip into two or more parts, each fabricated at a separate foundry. No one foundry sees the entire design, hindering its ability to thieve the chip’s IP or (as we discuss) maliciously modify the chip. Building upon this intuitive idea, this chapter describes relevant threat models for split manufacturing, a quantitative notion of security for split manufacturing, and techniques to trade off “cost” for security.

Original languageEnglish (US)
Title of host publicationHardware Protection through Obfuscation
PublisherSpringer International Publishing
Pages243-262
Number of pages20
ISBN (Electronic)9783319490199
ISBN (Print)9783319490182
DOIs
StatePublished - Jan 1 2017

Fingerprint

Foundries
Hardware
Costs

Keywords

  • 3D integration
  • BEOL
  • FEOL
  • Hardware trojan
  • IP piracy
  • K-security
  • Proximity attack
  • Secure layout
  • Secure partitioning
  • Split manufacturing
  • Sub-graph isomorphism

ASJC Scopus subject areas

  • Engineering(all)
  • Computer Science(all)

Cite this

Garg, S., & Rajendran, J. J. V. (2017). Split manufacturing. In Hardware Protection through Obfuscation (pp. 243-262). Springer International Publishing. https://doi.org/10.1007/978-3-319-49019-9_10

Split manufacturing. / Garg, Siddharth; Rajendran, Jeyavijayan J V.

Hardware Protection through Obfuscation. Springer International Publishing, 2017. p. 243-262.

Research output: Chapter in Book/Report/Conference proceedingChapter

Garg, S & Rajendran, JJV 2017, Split manufacturing. in Hardware Protection through Obfuscation. Springer International Publishing, pp. 243-262. https://doi.org/10.1007/978-3-319-49019-9_10
Garg S, Rajendran JJV. Split manufacturing. In Hardware Protection through Obfuscation. Springer International Publishing. 2017. p. 243-262 https://doi.org/10.1007/978-3-319-49019-9_10
Garg, Siddharth ; Rajendran, Jeyavijayan J V. / Split manufacturing. Hardware Protection through Obfuscation. Springer International Publishing, 2017. pp. 243-262
@inbook{530d237067424ecdbb3207ef62f3f76d,
title = "Split manufacturing",
abstract = "This chapter discusses split manufacturing, a promising hardware obfuscation technique that partitions a chip into two or more parts, each fabricated at a separate foundry. No one foundry sees the entire design, hindering its ability to thieve the chip’s IP or (as we discuss) maliciously modify the chip. Building upon this intuitive idea, this chapter describes relevant threat models for split manufacturing, a quantitative notion of security for split manufacturing, and techniques to trade off “cost” for security.",
keywords = "3D integration, BEOL, FEOL, Hardware trojan, IP piracy, K-security, Proximity attack, Secure layout, Secure partitioning, Split manufacturing, Sub-graph isomorphism",
author = "Siddharth Garg and Rajendran, {Jeyavijayan J V}",
year = "2017",
month = "1",
day = "1",
doi = "10.1007/978-3-319-49019-9_10",
language = "English (US)",
isbn = "9783319490182",
pages = "243--262",
booktitle = "Hardware Protection through Obfuscation",
publisher = "Springer International Publishing",

}

TY - CHAP

T1 - Split manufacturing

AU - Garg, Siddharth

AU - Rajendran, Jeyavijayan J V

PY - 2017/1/1

Y1 - 2017/1/1

N2 - This chapter discusses split manufacturing, a promising hardware obfuscation technique that partitions a chip into two or more parts, each fabricated at a separate foundry. No one foundry sees the entire design, hindering its ability to thieve the chip’s IP or (as we discuss) maliciously modify the chip. Building upon this intuitive idea, this chapter describes relevant threat models for split manufacturing, a quantitative notion of security for split manufacturing, and techniques to trade off “cost” for security.

AB - This chapter discusses split manufacturing, a promising hardware obfuscation technique that partitions a chip into two or more parts, each fabricated at a separate foundry. No one foundry sees the entire design, hindering its ability to thieve the chip’s IP or (as we discuss) maliciously modify the chip. Building upon this intuitive idea, this chapter describes relevant threat models for split manufacturing, a quantitative notion of security for split manufacturing, and techniques to trade off “cost” for security.

KW - 3D integration

KW - BEOL

KW - FEOL

KW - Hardware trojan

KW - IP piracy

KW - K-security

KW - Proximity attack

KW - Secure layout

KW - Secure partitioning

KW - Split manufacturing

KW - Sub-graph isomorphism

UR - http://www.scopus.com/inward/record.url?scp=85015106580&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85015106580&partnerID=8YFLogxK

U2 - 10.1007/978-3-319-49019-9_10

DO - 10.1007/978-3-319-49019-9_10

M3 - Chapter

AN - SCOPUS:85015106580

SN - 9783319490182

SP - 243

EP - 262

BT - Hardware Protection through Obfuscation

PB - Springer International Publishing

ER -