Software-directed power-aware interconnection networks

Vassos Soteriou Soteriou, Noel Eisley, Li Shiuan Peh

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    Interconnection networks have been deployed as the communication fabric in a wide range of parallel computer systems. With recent technological trends allowing growing quantities of chip resources and faster clock rates, there have been prevailing concerns of increasing power consumption being a major limiting factor in the design of parallel computer systems, from multiprocessor SoCs to multi-chip embedded systems and parallel servers. To tackle this, power-aware networks must become inherent components of single-chip and multi-chip systems. On the hardware design side, while there has been some recent interconnection network power reduction research, especially targeted towards communication links, the techniques presented are ad hoc and are not tailored to the application running on the network. We show that with these ad hoc techniques, power savings and corresponding impact on network latency vary significantly from one application to the next - in many cases network performance can suffer severely. On the software side, extensive research on compile-time optimization has produced parallelizing compilers that can efficiently map an application onto hardware for high performance. However, research into power-aware parallelizing compilers is in its infancy; none addressed communication power. In this paper, we take the first steps towards tailoring applications' communication needs at run-time for low power. We propose software techniques that extend the flow of a parallelizing compiler in order to direct run-time network power optimization. We target network links, the dominant power consumer in these systems, allowing DVS instructions extracted during static compilation to orchestrate link voltage and frequency transitions for power savings during application runtime. Concurrently, a hardware online mechanism measures network congestion levels and adapts these off-line DVS settings to optimize network performance. Our simulations show that link power consumption can be greatly reduced by up to 76.3%, with a minor increase in network latency in the range of 0.23% to 6.78% across a number of benchmark suites running on three existing parallel architectures, from very fine-grained single-chip to coarse-grained multi-chip architectures.

    Original languageEnglish (US)
    Title of host publicationCASES 2005
    Subtitle of host publicationInternational Conference on Compilers, Architecture, and Synthesis for Embedded Systems
    Pages274-285
    Number of pages12
    StatePublished - Dec 23 2005
    EventCASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems - San Francisco, CA, United States
    Duration: Sep 24 2005Sep 27 2005

    Other

    OtherCASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
    CountryUnited States
    CitySan Francisco, CA
    Period9/24/059/27/05

    Fingerprint

    Network performance
    Hardware
    Communication
    Computer systems
    Electric power utilization
    Parallel architectures
    Embedded systems
    Telecommunication links
    Clocks
    Servers
    Electric potential

    Keywords

    • Communication links
    • Dynamic voltage scaling
    • Interconnection networks
    • Networks on-a-chip (NoC)
    • Simulation.
    • Software-directed power reduction

    ASJC Scopus subject areas

    • Engineering(all)

    Cite this

    Soteriou, V. S., Eisley, N., & Peh, L. S. (2005). Software-directed power-aware interconnection networks. In CASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (pp. 274-285)

    Software-directed power-aware interconnection networks. / Soteriou, Vassos Soteriou; Eisley, Noel; Peh, Li Shiuan.

    CASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. 2005. p. 274-285.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Soteriou, VS, Eisley, N & Peh, LS 2005, Software-directed power-aware interconnection networks. in CASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. pp. 274-285, CASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, San Francisco, CA, United States, 9/24/05.
    Soteriou VS, Eisley N, Peh LS. Software-directed power-aware interconnection networks. In CASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. 2005. p. 274-285
    Soteriou, Vassos Soteriou ; Eisley, Noel ; Peh, Li Shiuan. / Software-directed power-aware interconnection networks. CASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. 2005. pp. 274-285
    @inproceedings{d347912fb08e4987a59fc3c6fd4e7ba1,
    title = "Software-directed power-aware interconnection networks",
    abstract = "Interconnection networks have been deployed as the communication fabric in a wide range of parallel computer systems. With recent technological trends allowing growing quantities of chip resources and faster clock rates, there have been prevailing concerns of increasing power consumption being a major limiting factor in the design of parallel computer systems, from multiprocessor SoCs to multi-chip embedded systems and parallel servers. To tackle this, power-aware networks must become inherent components of single-chip and multi-chip systems. On the hardware design side, while there has been some recent interconnection network power reduction research, especially targeted towards communication links, the techniques presented are ad hoc and are not tailored to the application running on the network. We show that with these ad hoc techniques, power savings and corresponding impact on network latency vary significantly from one application to the next - in many cases network performance can suffer severely. On the software side, extensive research on compile-time optimization has produced parallelizing compilers that can efficiently map an application onto hardware for high performance. However, research into power-aware parallelizing compilers is in its infancy; none addressed communication power. In this paper, we take the first steps towards tailoring applications' communication needs at run-time for low power. We propose software techniques that extend the flow of a parallelizing compiler in order to direct run-time network power optimization. We target network links, the dominant power consumer in these systems, allowing DVS instructions extracted during static compilation to orchestrate link voltage and frequency transitions for power savings during application runtime. Concurrently, a hardware online mechanism measures network congestion levels and adapts these off-line DVS settings to optimize network performance. Our simulations show that link power consumption can be greatly reduced by up to 76.3{\%}, with a minor increase in network latency in the range of 0.23{\%} to 6.78{\%} across a number of benchmark suites running on three existing parallel architectures, from very fine-grained single-chip to coarse-grained multi-chip architectures.",
    keywords = "Communication links, Dynamic voltage scaling, Interconnection networks, Networks on-a-chip (NoC), Simulation., Software-directed power reduction",
    author = "Soteriou, {Vassos Soteriou} and Noel Eisley and Peh, {Li Shiuan}",
    year = "2005",
    month = "12",
    day = "23",
    language = "English (US)",
    isbn = "159593149X",
    pages = "274--285",
    booktitle = "CASES 2005",

    }

    TY - GEN

    T1 - Software-directed power-aware interconnection networks

    AU - Soteriou, Vassos Soteriou

    AU - Eisley, Noel

    AU - Peh, Li Shiuan

    PY - 2005/12/23

    Y1 - 2005/12/23

    N2 - Interconnection networks have been deployed as the communication fabric in a wide range of parallel computer systems. With recent technological trends allowing growing quantities of chip resources and faster clock rates, there have been prevailing concerns of increasing power consumption being a major limiting factor in the design of parallel computer systems, from multiprocessor SoCs to multi-chip embedded systems and parallel servers. To tackle this, power-aware networks must become inherent components of single-chip and multi-chip systems. On the hardware design side, while there has been some recent interconnection network power reduction research, especially targeted towards communication links, the techniques presented are ad hoc and are not tailored to the application running on the network. We show that with these ad hoc techniques, power savings and corresponding impact on network latency vary significantly from one application to the next - in many cases network performance can suffer severely. On the software side, extensive research on compile-time optimization has produced parallelizing compilers that can efficiently map an application onto hardware for high performance. However, research into power-aware parallelizing compilers is in its infancy; none addressed communication power. In this paper, we take the first steps towards tailoring applications' communication needs at run-time for low power. We propose software techniques that extend the flow of a parallelizing compiler in order to direct run-time network power optimization. We target network links, the dominant power consumer in these systems, allowing DVS instructions extracted during static compilation to orchestrate link voltage and frequency transitions for power savings during application runtime. Concurrently, a hardware online mechanism measures network congestion levels and adapts these off-line DVS settings to optimize network performance. Our simulations show that link power consumption can be greatly reduced by up to 76.3%, with a minor increase in network latency in the range of 0.23% to 6.78% across a number of benchmark suites running on three existing parallel architectures, from very fine-grained single-chip to coarse-grained multi-chip architectures.

    AB - Interconnection networks have been deployed as the communication fabric in a wide range of parallel computer systems. With recent technological trends allowing growing quantities of chip resources and faster clock rates, there have been prevailing concerns of increasing power consumption being a major limiting factor in the design of parallel computer systems, from multiprocessor SoCs to multi-chip embedded systems and parallel servers. To tackle this, power-aware networks must become inherent components of single-chip and multi-chip systems. On the hardware design side, while there has been some recent interconnection network power reduction research, especially targeted towards communication links, the techniques presented are ad hoc and are not tailored to the application running on the network. We show that with these ad hoc techniques, power savings and corresponding impact on network latency vary significantly from one application to the next - in many cases network performance can suffer severely. On the software side, extensive research on compile-time optimization has produced parallelizing compilers that can efficiently map an application onto hardware for high performance. However, research into power-aware parallelizing compilers is in its infancy; none addressed communication power. In this paper, we take the first steps towards tailoring applications' communication needs at run-time for low power. We propose software techniques that extend the flow of a parallelizing compiler in order to direct run-time network power optimization. We target network links, the dominant power consumer in these systems, allowing DVS instructions extracted during static compilation to orchestrate link voltage and frequency transitions for power savings during application runtime. Concurrently, a hardware online mechanism measures network congestion levels and adapts these off-line DVS settings to optimize network performance. Our simulations show that link power consumption can be greatly reduced by up to 76.3%, with a minor increase in network latency in the range of 0.23% to 6.78% across a number of benchmark suites running on three existing parallel architectures, from very fine-grained single-chip to coarse-grained multi-chip architectures.

    KW - Communication links

    KW - Dynamic voltage scaling

    KW - Interconnection networks

    KW - Networks on-a-chip (NoC)

    KW - Simulation.

    KW - Software-directed power reduction

    UR - http://www.scopus.com/inward/record.url?scp=29144475874&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=29144475874&partnerID=8YFLogxK

    M3 - Conference contribution

    SN - 159593149X

    SN - 9781595931498

    SP - 274

    EP - 285

    BT - CASES 2005

    ER -