Sneak-path testing of memristor-based memories

Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Memristors are an attractive option for use in future memory architectures due to their non-volatility, low power operation and compactness. Notwithstanding these advantages, memristors and memristor-based memories are prone to high defect densities due to the non-deterministic nature of nanoscale fabrication. As a first step, we will examine the defect mechanisms in memristors and develop efficient fault models. Next, the memory subsystem has to be tested. The typical approach to testing a memory subsystem entails testing one memory element at a time. This is time consuming and does not scale for dense, memristor-based memories. We propose an efficient testing technique to test memristor-based memories. The proposed scheme uses sneak-paths inherent in crossbar memories to test multiple memristors at the same time and thereby reduces the test time by ∼32%.

Original languageEnglish (US)
Title of host publicationProceedings - 26th International Conference on VLSI Design, VLSID 2013 - Concurrently with 12th International Conference on Embedded Systems Design, ES 2013
Pages386-391
Number of pages6
DOIs
StatePublished - 2013
Event2013 26th International Conference on VLSI Design, VLSID 2013 and 12th International Conference on Embedded Systems, ES 2013 - Pune, India
Duration: Jan 5 2013Jan 10 2013

Other

Other2013 26th International Conference on VLSI Design, VLSID 2013 and 12th International Conference on Embedded Systems, ES 2013
CountryIndia
CityPune
Period1/5/131/10/13

Fingerprint

Memristors
Data storage equipment
Testing
Memory architecture
Defect density
Fabrication
Defects

Keywords

  • Emerging memory technologies
  • Fault modeling
  • Memory testing
  • Metal-oxide memristors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Kannan, S., Rajendran, J., Karri, R., & Sinanoglu, O. (2013). Sneak-path testing of memristor-based memories. In Proceedings - 26th International Conference on VLSI Design, VLSID 2013 - Concurrently with 12th International Conference on Embedded Systems Design, ES 2013 (pp. 386-391). [6472671] https://doi.org/10.1109/VLSID.2013.219

Sneak-path testing of memristor-based memories. / Kannan, Sachhidh; Rajendran, Jeyavijayan; Karri, Ramesh; Sinanoglu, Ozgur.

Proceedings - 26th International Conference on VLSI Design, VLSID 2013 - Concurrently with 12th International Conference on Embedded Systems Design, ES 2013. 2013. p. 386-391 6472671.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kannan, S, Rajendran, J, Karri, R & Sinanoglu, O 2013, Sneak-path testing of memristor-based memories. in Proceedings - 26th International Conference on VLSI Design, VLSID 2013 - Concurrently with 12th International Conference on Embedded Systems Design, ES 2013., 6472671, pp. 386-391, 2013 26th International Conference on VLSI Design, VLSID 2013 and 12th International Conference on Embedded Systems, ES 2013, Pune, India, 1/5/13. https://doi.org/10.1109/VLSID.2013.219
Kannan S, Rajendran J, Karri R, Sinanoglu O. Sneak-path testing of memristor-based memories. In Proceedings - 26th International Conference on VLSI Design, VLSID 2013 - Concurrently with 12th International Conference on Embedded Systems Design, ES 2013. 2013. p. 386-391. 6472671 https://doi.org/10.1109/VLSID.2013.219
Kannan, Sachhidh ; Rajendran, Jeyavijayan ; Karri, Ramesh ; Sinanoglu, Ozgur. / Sneak-path testing of memristor-based memories. Proceedings - 26th International Conference on VLSI Design, VLSID 2013 - Concurrently with 12th International Conference on Embedded Systems Design, ES 2013. 2013. pp. 386-391
@inproceedings{57deea60eab148d4ba9f01e7e74889b9,
title = "Sneak-path testing of memristor-based memories",
abstract = "Memristors are an attractive option for use in future memory architectures due to their non-volatility, low power operation and compactness. Notwithstanding these advantages, memristors and memristor-based memories are prone to high defect densities due to the non-deterministic nature of nanoscale fabrication. As a first step, we will examine the defect mechanisms in memristors and develop efficient fault models. Next, the memory subsystem has to be tested. The typical approach to testing a memory subsystem entails testing one memory element at a time. This is time consuming and does not scale for dense, memristor-based memories. We propose an efficient testing technique to test memristor-based memories. The proposed scheme uses sneak-paths inherent in crossbar memories to test multiple memristors at the same time and thereby reduces the test time by ∼32{\%}.",
keywords = "Emerging memory technologies, Fault modeling, Memory testing, Metal-oxide memristors",
author = "Sachhidh Kannan and Jeyavijayan Rajendran and Ramesh Karri and Ozgur Sinanoglu",
year = "2013",
doi = "10.1109/VLSID.2013.219",
language = "English (US)",
isbn = "9780769548890",
pages = "386--391",
booktitle = "Proceedings - 26th International Conference on VLSI Design, VLSID 2013 - Concurrently with 12th International Conference on Embedded Systems Design, ES 2013",

}

TY - GEN

T1 - Sneak-path testing of memristor-based memories

AU - Kannan, Sachhidh

AU - Rajendran, Jeyavijayan

AU - Karri, Ramesh

AU - Sinanoglu, Ozgur

PY - 2013

Y1 - 2013

N2 - Memristors are an attractive option for use in future memory architectures due to their non-volatility, low power operation and compactness. Notwithstanding these advantages, memristors and memristor-based memories are prone to high defect densities due to the non-deterministic nature of nanoscale fabrication. As a first step, we will examine the defect mechanisms in memristors and develop efficient fault models. Next, the memory subsystem has to be tested. The typical approach to testing a memory subsystem entails testing one memory element at a time. This is time consuming and does not scale for dense, memristor-based memories. We propose an efficient testing technique to test memristor-based memories. The proposed scheme uses sneak-paths inherent in crossbar memories to test multiple memristors at the same time and thereby reduces the test time by ∼32%.

AB - Memristors are an attractive option for use in future memory architectures due to their non-volatility, low power operation and compactness. Notwithstanding these advantages, memristors and memristor-based memories are prone to high defect densities due to the non-deterministic nature of nanoscale fabrication. As a first step, we will examine the defect mechanisms in memristors and develop efficient fault models. Next, the memory subsystem has to be tested. The typical approach to testing a memory subsystem entails testing one memory element at a time. This is time consuming and does not scale for dense, memristor-based memories. We propose an efficient testing technique to test memristor-based memories. The proposed scheme uses sneak-paths inherent in crossbar memories to test multiple memristors at the same time and thereby reduces the test time by ∼32%.

KW - Emerging memory technologies

KW - Fault modeling

KW - Memory testing

KW - Metal-oxide memristors

UR - http://www.scopus.com/inward/record.url?scp=84875597204&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84875597204&partnerID=8YFLogxK

U2 - 10.1109/VLSID.2013.219

DO - 10.1109/VLSID.2013.219

M3 - Conference contribution

SN - 9780769548890

SP - 386

EP - 391

BT - Proceedings - 26th International Conference on VLSI Design, VLSID 2013 - Concurrently with 12th International Conference on Embedded Systems Design, ES 2013

ER -