Sneak path testing and fault modeling for multilevel memristor-based memories

Sachhidh Kannan, Ramesh Karri, Ozgur Sinanoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Memristors are an attractive option for use in future memory architectures due to their non-volatility, low power operation, compactness and ability to store multiple bits in a single cell. Notwithstanding these advantages, memristors and memristor-based memories are prone to high defect densities due to the non-deterministic nature of nanoscale fabrication. As a first step, we will examine the defect mechanisms in multi-level cells (MLC) using memristors and develop efficient fault models. We will also investigate efficient test techniques for multi-level memristor based memories. The typical approach to testing a memory subsystem entails testing one memory cell at a time. This is time consuming and does not scale for dense, memristor-based memories. We propose an efficient testing technique to test memristor-based memories. The proposed scheme uses sneak paths inherent in crossbar memories to test multiple memristors at the same time and thereby reduces the test time by 27%.

Original languageEnglish (US)
Title of host publication2013 IEEE 31st International Conference on Computer Design, ICCD 2013
PublisherIEEE Computer Society
Pages215-220
Number of pages6
ISBN (Print)9781479929870
DOIs
StatePublished - 2013
Event2013 IEEE 31st International Conference on Computer Design, ICCD 2013 - Asheville, NC, United States
Duration: Oct 6 2013Oct 9 2013

Other

Other2013 IEEE 31st International Conference on Computer Design, ICCD 2013
CountryUnited States
CityAsheville, NC
Period10/6/1310/9/13

Fingerprint

Memristors
Data storage equipment
Testing
Memory architecture
Defect density
Fabrication
Defects

Keywords

  • emerging memory technologies
  • fault modeling
  • memory testing
  • metal-oxide memristors

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Hardware and Architecture

Cite this

Kannan, S., Karri, R., & Sinanoglu, O. (2013). Sneak path testing and fault modeling for multilevel memristor-based memories. In 2013 IEEE 31st International Conference on Computer Design, ICCD 2013 (pp. 215-220). [6657045] IEEE Computer Society. https://doi.org/10.1109/ICCD.2013.6657045

Sneak path testing and fault modeling for multilevel memristor-based memories. / Kannan, Sachhidh; Karri, Ramesh; Sinanoglu, Ozgur.

2013 IEEE 31st International Conference on Computer Design, ICCD 2013. IEEE Computer Society, 2013. p. 215-220 6657045.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kannan, S, Karri, R & Sinanoglu, O 2013, Sneak path testing and fault modeling for multilevel memristor-based memories. in 2013 IEEE 31st International Conference on Computer Design, ICCD 2013., 6657045, IEEE Computer Society, pp. 215-220, 2013 IEEE 31st International Conference on Computer Design, ICCD 2013, Asheville, NC, United States, 10/6/13. https://doi.org/10.1109/ICCD.2013.6657045
Kannan S, Karri R, Sinanoglu O. Sneak path testing and fault modeling for multilevel memristor-based memories. In 2013 IEEE 31st International Conference on Computer Design, ICCD 2013. IEEE Computer Society. 2013. p. 215-220. 6657045 https://doi.org/10.1109/ICCD.2013.6657045
Kannan, Sachhidh ; Karri, Ramesh ; Sinanoglu, Ozgur. / Sneak path testing and fault modeling for multilevel memristor-based memories. 2013 IEEE 31st International Conference on Computer Design, ICCD 2013. IEEE Computer Society, 2013. pp. 215-220
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