Abstract
Memristors are an attractive option for use in future memory architectures due to their non-volatility, low power operation, compactness and ability to store multiple bits in a single cell. Notwithstanding these advantages, memristors and memristor-based memories are prone to high defect densities due to the non-deterministic nature of nanoscale fabrication. As a first step, we will examine the defect mechanisms in multi-level cells (MLC) using memristors and develop efficient fault models. We will also investigate efficient test techniques for multi-level memristor based memories. The typical approach to testing a memory subsystem entails testing one memory cell at a time. This is time consuming and does not scale for dense, memristor-based memories. We propose an efficient testing technique to test memristor-based memories. The proposed scheme uses sneak paths inherent in crossbar memories to test multiple memristors at the same time and thereby reduces the test time by 27%.
| Original language | English (US) |
|---|---|
| Title of host publication | 2013 IEEE 31st International Conference on Computer Design, ICCD 2013 |
| Publisher | IEEE Computer Society |
| Pages | 215-220 |
| Number of pages | 6 |
| ISBN (Print) | 9781479929870 |
| DOIs | |
| State | Published - 2013 |
| Event | 2013 IEEE 31st International Conference on Computer Design, ICCD 2013 - Asheville, NC, United States Duration: Oct 6 2013 → Oct 9 2013 |
Other
| Other | 2013 IEEE 31st International Conference on Computer Design, ICCD 2013 |
|---|---|
| Country | United States |
| City | Asheville, NC |
| Period | 10/6/13 → 10/9/13 |
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Keywords
- emerging memory technologies
- fault modeling
- memory testing
- metal-oxide memristors
ASJC Scopus subject areas
- Computer Graphics and Computer-Aided Design
- Hardware and Architecture
Cite this
Sneak path testing and fault modeling for multilevel memristor-based memories. / Kannan, Sachhidh; Karri, Ramesh; Sinanoglu, Ozgur.
2013 IEEE 31st International Conference on Computer Design, ICCD 2013. IEEE Computer Society, 2013. p. 215-220 6657045.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Sneak path testing and fault modeling for multilevel memristor-based memories
AU - Kannan, Sachhidh
AU - Karri, Ramesh
AU - Sinanoglu, Ozgur
PY - 2013
Y1 - 2013
N2 - Memristors are an attractive option for use in future memory architectures due to their non-volatility, low power operation, compactness and ability to store multiple bits in a single cell. Notwithstanding these advantages, memristors and memristor-based memories are prone to high defect densities due to the non-deterministic nature of nanoscale fabrication. As a first step, we will examine the defect mechanisms in multi-level cells (MLC) using memristors and develop efficient fault models. We will also investigate efficient test techniques for multi-level memristor based memories. The typical approach to testing a memory subsystem entails testing one memory cell at a time. This is time consuming and does not scale for dense, memristor-based memories. We propose an efficient testing technique to test memristor-based memories. The proposed scheme uses sneak paths inherent in crossbar memories to test multiple memristors at the same time and thereby reduces the test time by 27%.
AB - Memristors are an attractive option for use in future memory architectures due to their non-volatility, low power operation, compactness and ability to store multiple bits in a single cell. Notwithstanding these advantages, memristors and memristor-based memories are prone to high defect densities due to the non-deterministic nature of nanoscale fabrication. As a first step, we will examine the defect mechanisms in multi-level cells (MLC) using memristors and develop efficient fault models. We will also investigate efficient test techniques for multi-level memristor based memories. The typical approach to testing a memory subsystem entails testing one memory cell at a time. This is time consuming and does not scale for dense, memristor-based memories. We propose an efficient testing technique to test memristor-based memories. The proposed scheme uses sneak paths inherent in crossbar memories to test multiple memristors at the same time and thereby reduces the test time by 27%.
KW - emerging memory technologies
KW - fault modeling
KW - memory testing
KW - metal-oxide memristors
UR - http://www.scopus.com/inward/record.url?scp=84892512372&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84892512372&partnerID=8YFLogxK
U2 - 10.1109/ICCD.2013.6657045
DO - 10.1109/ICCD.2013.6657045
M3 - Conference contribution
SN - 9781479929870
SP - 215
EP - 220
BT - 2013 IEEE 31st International Conference on Computer Design, ICCD 2013
PB - IEEE Computer Society
ER -