Sizing a packet reassembly buffer at a host computer in an ATM network

D.E. Smith, Jonathan Chao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Original languageEnglish (US)
Title of host publicationSecond Bellcore Symposium on Performance Modeling, Livingston, NJ, November 1992
StatePublished - 1992

Cite this

Smith, D. E., & Chao, J. (1992). Sizing a packet reassembly buffer at a host computer in an ATM network. In Second Bellcore Symposium on Performance Modeling, Livingston, NJ, November 1992

Sizing a packet reassembly buffer at a host computer in an ATM network. / Smith, D.E.; Chao, Jonathan.

Second Bellcore Symposium on Performance Modeling, Livingston, NJ, November 1992. 1992.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Smith, DE & Chao, J 1992, Sizing a packet reassembly buffer at a host computer in an ATM network. in Second Bellcore Symposium on Performance Modeling, Livingston, NJ, November 1992.
Smith DE, Chao J. Sizing a packet reassembly buffer at a host computer in an ATM network. In Second Bellcore Symposium on Performance Modeling, Livingston, NJ, November 1992. 1992
Smith, D.E. ; Chao, Jonathan. / Sizing a packet reassembly buffer at a host computer in an ATM network. Second Bellcore Symposium on Performance Modeling, Livingston, NJ, November 1992. 1992.
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