Simultaneous scheduling and binding for power minimization during microarchitecture synthesis

Aurobindo Dasgupta, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Sub-micron technologies and the increasing size and complexity of integrated components have aggravated the effect of long interconnects and buses, compared to that of gates, on the overall performance, and energy of systems. Consequently, we propose a RT level design technique to reduce the energy dissipated in switching of the buses (≈40% of the on-chip power) in the synthesized microarchitectures. This is accomplished by judiciously binding/scheduling data transfers in a Control Data Flow Graph (CDFG) onto buses in the design. The algorithm considers (i) correlations between data transfers, (ii) constraints on system performance, and (iii) constraints on the number of buses. Simulations on benchmarks show that best-energy designs are up to 75% energy-efficient vis-a-vis the worst-energy designs. Further, best-energy designs are up to 45% more energy-efficient than the best-delay designs.

Original languageEnglish (US)
Title of host publicationProceedings of the International Symposium on Low Power Design
PublisherACM
Pages69-74
Number of pages6
StatePublished - 1995
EventProceedings of the 1995 International Symposium on Low Power Design - Dana Point, CA, USA
Duration: Apr 23 1995Apr 26 1995

Other

OtherProceedings of the 1995 International Symposium on Low Power Design
CityDana Point, CA, USA
Period4/23/954/26/95

ASJC Scopus subject areas

  • Engineering(all)

Fingerprint Dive into the research topics of 'Simultaneous scheduling and binding for power minimization during microarchitecture synthesis'. Together they form a unique fingerprint.

  • Cite this

    Dasgupta, A., & Karri, R. (1995). Simultaneous scheduling and binding for power minimization during microarchitecture synthesis. In Proceedings of the International Symposium on Low Power Design (pp. 69-74). ACM.