Security vulnerabilities of emerging nonvolatile main memories and countermeasures

Sachhidh Kannan, Naghmeh Karimi, Ozgur Sinanoglu, Ramesh Karri

Research output: Contribution to journalArticle

Abstract

Emerging nonvolatile memory devices such as phase change memories and memristors are replacing SRAM and DRAM. However, nonvolatile main memories (NVMM) are susceptible to probing attacks even when powered down. This way, they may compromise sensitive data such as passwords and keys that reside in the NVMM. To eliminate this vulnerability, we propose sneak-path encryption (SPE), a hardware intrinsic encryption technique for memristor-based NVMMs. SPE is instruction set architecture independent and has minimal impact on performance. SPE exploits the physical parameters, such as sneak-paths in crossbar memories, to encrypt the data stored in a memristor-based NVMM. SPE is resilient to a number of attacks that may be performed on NVMMs. We use a cycle accurate simulator to evaluate the performance impact of SPE-based NVMM and compare against other security techniques. SPE can secure an NVMM with a ∼1.3% performance overhead.

Original languageEnglish (US)
Article number6952995
Pages (from-to)2-15
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume34
Issue number1
DOIs
StatePublished - Jan 1 2015

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Cryptography
Data storage equipment
Memristors
Phase change memory
Dynamic random access storage
Static random access storage
Computer hardware
Simulators

Keywords

  • Encryption
  • hardware security
  • memory security
  • memristor
  • RRAM

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Graphics and Computer-Aided Design
  • Software

Cite this

Security vulnerabilities of emerging nonvolatile main memories and countermeasures. / Kannan, Sachhidh; Karimi, Naghmeh; Sinanoglu, Ozgur; Karri, Ramesh.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, No. 1, 6952995, 01.01.2015, p. 2-15.

Research output: Contribution to journalArticle

@article{4ba6f46cf4cd45049cf59f5f77005703,
title = "Security vulnerabilities of emerging nonvolatile main memories and countermeasures",
abstract = "Emerging nonvolatile memory devices such as phase change memories and memristors are replacing SRAM and DRAM. However, nonvolatile main memories (NVMM) are susceptible to probing attacks even when powered down. This way, they may compromise sensitive data such as passwords and keys that reside in the NVMM. To eliminate this vulnerability, we propose sneak-path encryption (SPE), a hardware intrinsic encryption technique for memristor-based NVMMs. SPE is instruction set architecture independent and has minimal impact on performance. SPE exploits the physical parameters, such as sneak-paths in crossbar memories, to encrypt the data stored in a memristor-based NVMM. SPE is resilient to a number of attacks that may be performed on NVMMs. We use a cycle accurate simulator to evaluate the performance impact of SPE-based NVMM and compare against other security techniques. SPE can secure an NVMM with a ∼1.3{\%} performance overhead.",
keywords = "Encryption, hardware security, memory security, memristor, RRAM",
author = "Sachhidh Kannan and Naghmeh Karimi and Ozgur Sinanoglu and Ramesh Karri",
year = "2015",
month = "1",
day = "1",
doi = "10.1109/TCAD.2014.2369741",
language = "English (US)",
volume = "34",
pages = "2--15",
journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",
issn = "0278-0070",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "1",

}

TY - JOUR

T1 - Security vulnerabilities of emerging nonvolatile main memories and countermeasures

AU - Kannan, Sachhidh

AU - Karimi, Naghmeh

AU - Sinanoglu, Ozgur

AU - Karri, Ramesh

PY - 2015/1/1

Y1 - 2015/1/1

N2 - Emerging nonvolatile memory devices such as phase change memories and memristors are replacing SRAM and DRAM. However, nonvolatile main memories (NVMM) are susceptible to probing attacks even when powered down. This way, they may compromise sensitive data such as passwords and keys that reside in the NVMM. To eliminate this vulnerability, we propose sneak-path encryption (SPE), a hardware intrinsic encryption technique for memristor-based NVMMs. SPE is instruction set architecture independent and has minimal impact on performance. SPE exploits the physical parameters, such as sneak-paths in crossbar memories, to encrypt the data stored in a memristor-based NVMM. SPE is resilient to a number of attacks that may be performed on NVMMs. We use a cycle accurate simulator to evaluate the performance impact of SPE-based NVMM and compare against other security techniques. SPE can secure an NVMM with a ∼1.3% performance overhead.

AB - Emerging nonvolatile memory devices such as phase change memories and memristors are replacing SRAM and DRAM. However, nonvolatile main memories (NVMM) are susceptible to probing attacks even when powered down. This way, they may compromise sensitive data such as passwords and keys that reside in the NVMM. To eliminate this vulnerability, we propose sneak-path encryption (SPE), a hardware intrinsic encryption technique for memristor-based NVMMs. SPE is instruction set architecture independent and has minimal impact on performance. SPE exploits the physical parameters, such as sneak-paths in crossbar memories, to encrypt the data stored in a memristor-based NVMM. SPE is resilient to a number of attacks that may be performed on NVMMs. We use a cycle accurate simulator to evaluate the performance impact of SPE-based NVMM and compare against other security techniques. SPE can secure an NVMM with a ∼1.3% performance overhead.

KW - Encryption

KW - hardware security

KW - memory security

KW - memristor

KW - RRAM

UR - http://www.scopus.com/inward/record.url?scp=84919784754&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84919784754&partnerID=8YFLogxK

U2 - 10.1109/TCAD.2014.2369741

DO - 10.1109/TCAD.2014.2369741

M3 - Article

AN - SCOPUS:84919784754

VL - 34

SP - 2

EP - 15

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

SN - 0278-0070

IS - 1

M1 - 6952995

ER -