Security verification of 3rd party intellectual property cores for information leakage

Jeyavijayan Rajendran, A Dhandayuthapany, Ramesh Karri, V Vedula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Original languageEnglish (US)
Title of host publicationProceedings of IEEE VLSI Design
StatePublished - Jan 2016

Cite this

Rajendran, J., Dhandayuthapany, A., Karri, R., & Vedula, V. (2016). Security verification of 3rd party intellectual property cores for information leakage. In Proceedings of IEEE VLSI Design

Security verification of 3rd party intellectual property cores for information leakage. / Rajendran, Jeyavijayan; Dhandayuthapany, A; Karri, Ramesh; Vedula, V.

Proceedings of IEEE VLSI Design. 2016.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rajendran, J, Dhandayuthapany, A, Karri, R & Vedula, V 2016, Security verification of 3rd party intellectual property cores for information leakage. in Proceedings of IEEE VLSI Design.
Rajendran J, Dhandayuthapany A, Karri R, Vedula V. Security verification of 3rd party intellectual property cores for information leakage. In Proceedings of IEEE VLSI Design. 2016
Rajendran, Jeyavijayan ; Dhandayuthapany, A ; Karri, Ramesh ; Vedula, V. / Security verification of 3rd party intellectual property cores for information leakage. Proceedings of IEEE VLSI Design. 2016.
@inproceedings{da9441461a2a43c19c3e2e7cdc6b5b10,
title = "Security verification of 3rd party intellectual property cores for information leakage",
author = "Jeyavijayan Rajendran and A Dhandayuthapany and Ramesh Karri and V Vedula",
year = "2016",
month = "1",
language = "English (US)",
booktitle = "Proceedings of IEEE VLSI Design",

}

TY - GEN

T1 - Security verification of 3rd party intellectual property cores for information leakage

AU - Rajendran, Jeyavijayan

AU - Dhandayuthapany, A

AU - Karri, Ramesh

AU - Vedula, V

PY - 2016/1

Y1 - 2016/1

M3 - Conference contribution

BT - Proceedings of IEEE VLSI Design

ER -