Security-aware SoC test access mechanisms

Kurt Rosenfeld, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Test access mechanisms are critical components in digital systems. They affect not only production and operational economics, but also system security. We propose a security enhancement for system-on-chip (SoC) test access that addresses the threat posed by untrustworthy cores. The scheme maintains the economy of shared wiring (bus or daisy-chain) while achieving most of the security benefits of star-topology test access wiring. Using the proposed scheme, the tester is able to establish distinct cryptographic session keys with each of the cores, significantly reducing the exposure in cases where one or more of the cores contains malicious or otherwise untrustworthy logic. The proposed scheme is out of the functional path and does not affect functional timing or power consumption.

Original languageEnglish (US)
Title of host publicationProceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011
Pages100-104
Number of pages5
DOIs
StatePublished - 2011
Event2011 29th IEEE VLSI Test Symposium, VTS 2011 - Dana Point, CA, United States
Duration: May 1 2011May 5 2011

Other

Other2011 29th IEEE VLSI Test Symposium, VTS 2011
CountryUnited States
CityDana Point, CA
Period5/1/115/5/11

Fingerprint

Electric wiring
Security systems
Stars
Electric power utilization
Topology
Economics
System-on-chip

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications

Cite this

Rosenfeld, K., & Karri, R. (2011). Security-aware SoC test access mechanisms. In Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011 (pp. 100-104). [5783765] https://doi.org/10.1109/VTS.2011.5783765

Security-aware SoC test access mechanisms. / Rosenfeld, Kurt; Karri, Ramesh.

Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011. 2011. p. 100-104 5783765.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rosenfeld, K & Karri, R 2011, Security-aware SoC test access mechanisms. in Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011., 5783765, pp. 100-104, 2011 29th IEEE VLSI Test Symposium, VTS 2011, Dana Point, CA, United States, 5/1/11. https://doi.org/10.1109/VTS.2011.5783765
Rosenfeld K, Karri R. Security-aware SoC test access mechanisms. In Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011. 2011. p. 100-104. 5783765 https://doi.org/10.1109/VTS.2011.5783765
Rosenfeld, Kurt ; Karri, Ramesh. / Security-aware SoC test access mechanisms. Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011. 2011. pp. 100-104
@inproceedings{29502a37312b4ea8a5c3239e071db9e5,
title = "Security-aware SoC test access mechanisms",
abstract = "Test access mechanisms are critical components in digital systems. They affect not only production and operational economics, but also system security. We propose a security enhancement for system-on-chip (SoC) test access that addresses the threat posed by untrustworthy cores. The scheme maintains the economy of shared wiring (bus or daisy-chain) while achieving most of the security benefits of star-topology test access wiring. Using the proposed scheme, the tester is able to establish distinct cryptographic session keys with each of the cores, significantly reducing the exposure in cases where one or more of the cores contains malicious or otherwise untrustworthy logic. The proposed scheme is out of the functional path and does not affect functional timing or power consumption.",
author = "Kurt Rosenfeld and Ramesh Karri",
year = "2011",
doi = "10.1109/VTS.2011.5783765",
language = "English (US)",
isbn = "9781612846552",
pages = "100--104",
booktitle = "Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011",

}

TY - GEN

T1 - Security-aware SoC test access mechanisms

AU - Rosenfeld, Kurt

AU - Karri, Ramesh

PY - 2011

Y1 - 2011

N2 - Test access mechanisms are critical components in digital systems. They affect not only production and operational economics, but also system security. We propose a security enhancement for system-on-chip (SoC) test access that addresses the threat posed by untrustworthy cores. The scheme maintains the economy of shared wiring (bus or daisy-chain) while achieving most of the security benefits of star-topology test access wiring. Using the proposed scheme, the tester is able to establish distinct cryptographic session keys with each of the cores, significantly reducing the exposure in cases where one or more of the cores contains malicious or otherwise untrustworthy logic. The proposed scheme is out of the functional path and does not affect functional timing or power consumption.

AB - Test access mechanisms are critical components in digital systems. They affect not only production and operational economics, but also system security. We propose a security enhancement for system-on-chip (SoC) test access that addresses the threat posed by untrustworthy cores. The scheme maintains the economy of shared wiring (bus or daisy-chain) while achieving most of the security benefits of star-topology test access wiring. Using the proposed scheme, the tester is able to establish distinct cryptographic session keys with each of the cores, significantly reducing the exposure in cases where one or more of the cores contains malicious or otherwise untrustworthy logic. The proposed scheme is out of the functional path and does not affect functional timing or power consumption.

UR - http://www.scopus.com/inward/record.url?scp=79959627825&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79959627825&partnerID=8YFLogxK

U2 - 10.1109/VTS.2011.5783765

DO - 10.1109/VTS.2011.5783765

M3 - Conference contribution

AN - SCOPUS:79959627825

SN - 9781612846552

SP - 100

EP - 104

BT - Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011

ER -