Security-aware SoC test access mechanisms

Kurt Rosenfeld, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Test access mechanisms are critical components in digital systems. They affect not only production and operational economics, but also system security. We propose a security enhancement for system-on-chip (SoC) test access that addresses the threat posed by untrustworthy cores. The scheme maintains the economy of shared wiring (bus or daisy-chain) while achieving most of the security benefits of star-topology test access wiring. Using the proposed scheme, the tester is able to establish distinct cryptographic session keys with each of the cores, significantly reducing the exposure in cases where one or more of the cores contains malicious or otherwise untrustworthy logic. The proposed scheme is out of the functional path and does not affect functional timing or power consumption.

Original languageEnglish (US)
Title of host publicationProceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011
Pages100-104
Number of pages5
DOIs
StatePublished - Jul 1 2011
Event2011 29th IEEE VLSI Test Symposium, VTS 2011 - Dana Point, CA, United States
Duration: May 1 2011May 5 2011

Publication series

NameProceedings of the IEEE VLSI Test Symposium

Other

Other2011 29th IEEE VLSI Test Symposium, VTS 2011
CountryUnited States
CityDana Point, CA
Period5/1/115/5/11

    Fingerprint

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

Rosenfeld, K., & Karri, R. (2011). Security-aware SoC test access mechanisms. In Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011 (pp. 100-104). [5783765] (Proceedings of the IEEE VLSI Test Symposium). https://doi.org/10.1109/VTS.2011.5783765