Securing processors against insider attacks: A circuit-microarchitecture co-design approach

Jeyavijayan Rajendran, Arun Karthik Kanuparthi, Ramesh Karri, Mohamed Zahran, Sateesh K. Addepalli, Gaston Ormazabal

Research output: Contribution to journalArticle

Abstract

A joint circuit-architecture-level design approach is proposed that helps in preventing or detecting Trojan attacks. The performance impact of processor encryption depends on how often the security module is used. If a security module checks the instructions often, then processor encryption will have a high performance impact. The key size used for encryption increases as the detection sensitivity of detection technique increases. Apart from design size, power consumption and path-delays can also be used as metrics for detection sensitivity of a detection technique. Encrypting the entire pipeline will significantly impact processor's performance. Hence, we encrypt only some of the pipeline units depending up on the security modules in the processor. The TrustNet and DataWatch security modules are distributed, and hence multiple units are encrypted.

Original languageEnglish (US)
Article number6472275
Pages (from-to)35-44
Number of pages10
JournalIEEE Design and Test
Volume30
Issue number2
DOIs
StatePublished - 2013

Fingerprint

Cryptography
Networks (circuits)
Pipelines
Electric power utilization

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

Cite this

Rajendran, J., Kanuparthi, A. K., Karri, R., Zahran, M., Addepalli, S. K., & Ormazabal, G. (2013). Securing processors against insider attacks: A circuit-microarchitecture co-design approach. IEEE Design and Test, 30(2), 35-44. [6472275]. https://doi.org/10.1109/MDAT.2013.2249554

Securing processors against insider attacks : A circuit-microarchitecture co-design approach. / Rajendran, Jeyavijayan; Kanuparthi, Arun Karthik; Karri, Ramesh; Zahran, Mohamed; Addepalli, Sateesh K.; Ormazabal, Gaston.

In: IEEE Design and Test, Vol. 30, No. 2, 6472275, 2013, p. 35-44.

Research output: Contribution to journalArticle

Rajendran, J, Kanuparthi, AK, Karri, R, Zahran, M, Addepalli, SK & Ormazabal, G 2013, 'Securing processors against insider attacks: A circuit-microarchitecture co-design approach', IEEE Design and Test, vol. 30, no. 2, 6472275, pp. 35-44. https://doi.org/10.1109/MDAT.2013.2249554
Rajendran, Jeyavijayan ; Kanuparthi, Arun Karthik ; Karri, Ramesh ; Zahran, Mohamed ; Addepalli, Sateesh K. ; Ormazabal, Gaston. / Securing processors against insider attacks : A circuit-microarchitecture co-design approach. In: IEEE Design and Test. 2013 ; Vol. 30, No. 2. pp. 35-44.
@article{737820391641478e91c3a8735347db58,
title = "Securing processors against insider attacks: A circuit-microarchitecture co-design approach",
abstract = "A joint circuit-architecture-level design approach is proposed that helps in preventing or detecting Trojan attacks. The performance impact of processor encryption depends on how often the security module is used. If a security module checks the instructions often, then processor encryption will have a high performance impact. The key size used for encryption increases as the detection sensitivity of detection technique increases. Apart from design size, power consumption and path-delays can also be used as metrics for detection sensitivity of a detection technique. Encrypting the entire pipeline will significantly impact processor's performance. Hence, we encrypt only some of the pipeline units depending up on the security modules in the processor. The TrustNet and DataWatch security modules are distributed, and hence multiple units are encrypted.",
author = "Jeyavijayan Rajendran and Kanuparthi, {Arun Karthik} and Ramesh Karri and Mohamed Zahran and Addepalli, {Sateesh K.} and Gaston Ormazabal",
year = "2013",
doi = "10.1109/MDAT.2013.2249554",
language = "English (US)",
volume = "30",
pages = "35--44",
journal = "IEEE Design and Test",
issn = "2168-2356",
publisher = "IEEE Computer Society",
number = "2",

}

TY - JOUR

T1 - Securing processors against insider attacks

T2 - A circuit-microarchitecture co-design approach

AU - Rajendran, Jeyavijayan

AU - Kanuparthi, Arun Karthik

AU - Karri, Ramesh

AU - Zahran, Mohamed

AU - Addepalli, Sateesh K.

AU - Ormazabal, Gaston

PY - 2013

Y1 - 2013

N2 - A joint circuit-architecture-level design approach is proposed that helps in preventing or detecting Trojan attacks. The performance impact of processor encryption depends on how often the security module is used. If a security module checks the instructions often, then processor encryption will have a high performance impact. The key size used for encryption increases as the detection sensitivity of detection technique increases. Apart from design size, power consumption and path-delays can also be used as metrics for detection sensitivity of a detection technique. Encrypting the entire pipeline will significantly impact processor's performance. Hence, we encrypt only some of the pipeline units depending up on the security modules in the processor. The TrustNet and DataWatch security modules are distributed, and hence multiple units are encrypted.

AB - A joint circuit-architecture-level design approach is proposed that helps in preventing or detecting Trojan attacks. The performance impact of processor encryption depends on how often the security module is used. If a security module checks the instructions often, then processor encryption will have a high performance impact. The key size used for encryption increases as the detection sensitivity of detection technique increases. Apart from design size, power consumption and path-delays can also be used as metrics for detection sensitivity of a detection technique. Encrypting the entire pipeline will significantly impact processor's performance. Hence, we encrypt only some of the pipeline units depending up on the security modules in the processor. The TrustNet and DataWatch security modules are distributed, and hence multiple units are encrypted.

UR - http://www.scopus.com/inward/record.url?scp=84898832558&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84898832558&partnerID=8YFLogxK

U2 - 10.1109/MDAT.2013.2249554

DO - 10.1109/MDAT.2013.2249554

M3 - Article

AN - SCOPUS:84898832558

VL - 30

SP - 35

EP - 44

JO - IEEE Design and Test

JF - IEEE Design and Test

SN - 2168-2356

IS - 2

M1 - 6472275

ER -