Securing Hardware Accelerators

a New Challenge for High-Level Synthesis (Perspective Paper)

Christian Pilato, Siddharth Garg, Kaijie Wu, Ramesh Karri, Francesco Regazzoni

Research output: Contribution to journalArticle

Abstract

High-level synthesis (HLS) tools have made significant progress in the past few years, improving the design productivity for hardware accelerators and becoming mainstream in industry to create specialized System-on-Chip (SoC) architectures. Increasing the level of security of these heterogeneous architectures is becoming critical. However, state-of-the-art security countermeasures are still applied only to the code executing on the processor cores or manually implemented into the generated components, leading to suboptimal and sometimes even insecure designs. This paper discusses extensions to HLS tools for creating secure heterogeneous architectures.

Original languageEnglish (US)
JournalIEEE Embedded Systems Letters
DOIs
StateAccepted/In press - Nov 16 2017

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Particle accelerators
Hardware
Productivity
Industry
High level synthesis
System-on-chip

Keywords

  • Hardware
  • Hardware Security.
  • High-Level Synthesis
  • Microarchitecture
  • Optimization
  • Reverse engineering
  • Side-channel attacks
  • Tools

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Computer Science(all)

Cite this

Securing Hardware Accelerators : a New Challenge for High-Level Synthesis (Perspective Paper). / Pilato, Christian; Garg, Siddharth; Wu, Kaijie; Karri, Ramesh; Regazzoni, Francesco.

In: IEEE Embedded Systems Letters, 16.11.2017.

Research output: Contribution to journalArticle

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