Scan-in and scan-out transition co-optimization through modelling generalized serial transformations

Research output: Contribution to journalArticle

Abstract

Scan-based cores impose considerable test power challenges due to excessive switching activity during shift cycles. The consequent test power constraints force system-on-chip (SOC) designers to sacrifice parallelism among core tests, as exceeding power thresholds may damage the chip being tested. Reduction of test power for SOC cores can thus increase the number of cores that can be tested in parallel, improving significantly SOC test application time. In this paper, we propose a scan chain modification technique that inserts logic gates on the scan path. The consequent beneficial test data transformations are utilized to reduce the scan chain transitions during shift cycles and hence test power. We introduce a matrix band algebra that models the impact of logic gate insertion between scan cells on the test stimulus and response transformations realized. As we have successfully modeled the response transformations as well, the methodology we propose is capable of truly minimizing the overall test power. The test vectors and responses are analyzed in an intertwined manner, identifying the best possible scan chain modification, which is realized at minimal area cost. Experimental results justify the efficacy of the proposed methodology as well.

Original languageEnglish (US)
Pages (from-to)335-351
Number of pages17
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Volume24
Issue number4
DOIs
StatePublished - Aug 1 2008

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Logic gates
Algebra
System-on-chip
Costs

Keywords

  • Core-based testing
  • Design for testability
  • Scan chain modification
  • Scan power reduction
  • Serial transformations
  • Test power reduction

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

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title = "Scan-in and scan-out transition co-optimization through modelling generalized serial transformations",
abstract = "Scan-based cores impose considerable test power challenges due to excessive switching activity during shift cycles. The consequent test power constraints force system-on-chip (SOC) designers to sacrifice parallelism among core tests, as exceeding power thresholds may damage the chip being tested. Reduction of test power for SOC cores can thus increase the number of cores that can be tested in parallel, improving significantly SOC test application time. In this paper, we propose a scan chain modification technique that inserts logic gates on the scan path. The consequent beneficial test data transformations are utilized to reduce the scan chain transitions during shift cycles and hence test power. We introduce a matrix band algebra that models the impact of logic gate insertion between scan cells on the test stimulus and response transformations realized. As we have successfully modeled the response transformations as well, the methodology we propose is capable of truly minimizing the overall test power. The test vectors and responses are analyzed in an intertwined manner, identifying the best possible scan chain modification, which is realized at minimal area cost. Experimental results justify the efficacy of the proposed methodology as well.",
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