Scan chain hold-time violations: Can they be tolerated?

Ozgur Sinanoglu, Philip Schremmer

Research output: Contribution to journalArticle

Abstract

Scan chain hold-time violations may occur due to manufacturing defects or to errors in timing closure process during the physical design stage. The latter type of violations prohibits the test of manufactured chips, leading to a zero yield, although these chips with scan hold-time violations may be perfectly functional. In this paper, we propose a suite of techniques which enable the diagnosis and the tolerance of scan hold-time violations. The proposed diagnosis technique can be utilized for any scan chain hold-time violation in order to pinpoint, in minimal diagnosis application time, the cause of the violation. The proposed tolerance technique is more targeted towards violations that lead to systematic failure of parts; it enables the generation of test patterns to screen out the defective parts in the presence of scan hold-time violations, perfectly restoring the yield in a cost-effective manner. The techniques that we propose are non-intrusive, as they utilize only basic scan capabilities, and thus impose no design changes. We also extend this discussion for fast-to-rise and fast-to-fall errors, intermittent scan hold-time violations, and functional hold-time violations.

Original languageEnglish (US)
Article number4907215
Pages (from-to)815-826
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume17
Issue number6
DOIs
StatePublished - Jun 1 2009

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Keywords

  • Diagnosis
  • Hold-time violations
  • Scan chain errors
  • Tolerance

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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