Abstract
Ensuring a high manufacturing test quality of an integrated electronic circuit mandates the application of a large volume test set. Even if the test data can be fit into the memory of an external tester, the consequent increase in test application time reflects into elevated production costs. Test data compression solutions have been proposed to address the test time and data volume problem by storing and delivering the test data in a compressed format, and subsequently by expanding the data on-chip. In this paper, we propose a scan cell positioning methodology that accompanies a compression technique in order to boost the compression ratio, and squash the test data even further. While we present the application of the proposed approach in conjunction with the fan-out based decompression architecture, this approach can be extended for application along with other compression solutions as well. The experimental results also confirm the compression enhancement of the proposed methodology.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 939-948 |
| Number of pages | 10 |
| Journal | Journal of Computer Science and Technology |
| Volume | 24 |
| Issue number | 5 |
| DOIs | |
| State | Published - Sep 1 2009 |
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Keywords
- Scan architecture design
- Scan cell reordering
- Scan-based testing
- Test data compression
ASJC Scopus subject areas
- Theoretical Computer Science
- Software
- Hardware and Architecture
- Computer Science Applications
- Computational Theory and Mathematics
Cite this
Scan cell positioning for boosting the compression of fan-out networks. / Sinanoglu, Ozgur; Al-Mulla, Mohammed; Shunaiber, Noora A.; Orailoglu, Alex.
In: Journal of Computer Science and Technology, Vol. 24, No. 5, 01.09.2009, p. 939-948.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Scan cell positioning for boosting the compression of fan-out networks
AU - Sinanoglu, Ozgur
AU - Al-Mulla, Mohammed
AU - Shunaiber, Noora A.
AU - Orailoglu, Alex
PY - 2009/9/1
Y1 - 2009/9/1
N2 - Ensuring a high manufacturing test quality of an integrated electronic circuit mandates the application of a large volume test set. Even if the test data can be fit into the memory of an external tester, the consequent increase in test application time reflects into elevated production costs. Test data compression solutions have been proposed to address the test time and data volume problem by storing and delivering the test data in a compressed format, and subsequently by expanding the data on-chip. In this paper, we propose a scan cell positioning methodology that accompanies a compression technique in order to boost the compression ratio, and squash the test data even further. While we present the application of the proposed approach in conjunction with the fan-out based decompression architecture, this approach can be extended for application along with other compression solutions as well. The experimental results also confirm the compression enhancement of the proposed methodology.
AB - Ensuring a high manufacturing test quality of an integrated electronic circuit mandates the application of a large volume test set. Even if the test data can be fit into the memory of an external tester, the consequent increase in test application time reflects into elevated production costs. Test data compression solutions have been proposed to address the test time and data volume problem by storing and delivering the test data in a compressed format, and subsequently by expanding the data on-chip. In this paper, we propose a scan cell positioning methodology that accompanies a compression technique in order to boost the compression ratio, and squash the test data even further. While we present the application of the proposed approach in conjunction with the fan-out based decompression architecture, this approach can be extended for application along with other compression solutions as well. The experimental results also confirm the compression enhancement of the proposed methodology.
KW - Scan architecture design
KW - Scan cell reordering
KW - Scan-based testing
KW - Test data compression
UR - http://www.scopus.com/inward/record.url?scp=70349588478&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=70349588478&partnerID=8YFLogxK
U2 - 10.1007/s11390-009-9268-6
DO - 10.1007/s11390-009-9268-6
M3 - Article
VL - 24
SP - 939
EP - 948
JO - Journal of Computer Science and Technology
JF - Journal of Computer Science and Technology
SN - 1000-9000
IS - 5
ER -