RT-level fault simulation based on symbolic propagation

Ozgur Sinanoglu, A. Orailoglu

    Research output: Contribution to conferencePaper

    Abstract

    The rapid rise in size and complexity of VLSI circuits has stimulated a need to handle fault simulation at higher levels of abstraction. We outline an RT-level fault simulation technique that utilizes symbolic data to group fault effects. Experimental results show that the proposed methodology provides superior speed-ups and accurate fault coverages.

    Original languageEnglish (US)
    Pages240-245
    Number of pages6
    StatePublished - Jan 1 2001
    Event19th IEEE VLSI Test Symposium - Marina del Rey, CA, United States
    Duration: Apr 29 2001May 3 2001

    Other

    Other19th IEEE VLSI Test Symposium
    CountryUnited States
    CityMarina del Rey, CA
    Period4/29/015/3/01

    Fingerprint

    VLSI circuits

    ASJC Scopus subject areas

    • Computer Science Applications
    • Electrical and Electronic Engineering

    Cite this

    Sinanoglu, O., & Orailoglu, A. (2001). RT-level fault simulation based on symbolic propagation. 240-245. Paper presented at 19th IEEE VLSI Test Symposium, Marina del Rey, CA, United States.

    RT-level fault simulation based on symbolic propagation. / Sinanoglu, Ozgur; Orailoglu, A.

    2001. 240-245 Paper presented at 19th IEEE VLSI Test Symposium, Marina del Rey, CA, United States.

    Research output: Contribution to conferencePaper

    Sinanoglu, O & Orailoglu, A 2001, 'RT-level fault simulation based on symbolic propagation' Paper presented at 19th IEEE VLSI Test Symposium, Marina del Rey, CA, United States, 4/29/01 - 5/3/01, pp. 240-245.
    Sinanoglu O, Orailoglu A. RT-level fault simulation based on symbolic propagation. 2001. Paper presented at 19th IEEE VLSI Test Symposium, Marina del Rey, CA, United States.
    Sinanoglu, Ozgur ; Orailoglu, A. / RT-level fault simulation based on symbolic propagation. Paper presented at 19th IEEE VLSI Test Symposium, Marina del Rey, CA, United States.6 p.
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