Revisiting logic locking for reversible computing

Nimisha Limaye, Muhammad Yasin, Ozgur Sinanoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Analogous to CMOS circuits, we can expect attacks such as integrated circuit (IC) counterfeiting, piracy through reverse engineering (RE) or over-production, and insertion of hardware Trojans to be launched on emerging class of reversible circuits, which is a promising alternative to standard CMOS technology. In this paper, we explore the possibility of securing reversible circuits against IP piracy and RE attacks using state-of-the-art logic locking techniques. Our security analysis reveals that applying existing techniques as is on reversible circuits creates new vulnerabilities due to inherent reversible properties. We propose low overhead (around 0.013x for gate count, 0.0004x for T-count and 0.02x for quantum cost on average) defense strategies that overcome these vulnerabilities and protect the circuits from all known attacks.

Original languageEnglish (US)
Title of host publicationProceedings - 2019 IEEE European Test Symposium, ETS 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728111735
DOIs
StatePublished - May 1 2019
Event2019 IEEE European Test Symposium, ETS 2019 - Baden-Baden, Germany
Duration: May 27 2019May 31 2019

Publication series

NameProceedings of the European Test Workshop
Volume2019-May
ISSN (Print)1530-1877
ISSN (Electronic)1558-1780

Conference

Conference2019 IEEE European Test Symposium, ETS 2019
CountryGermany
CityBaden-Baden
Period5/27/195/31/19

Fingerprint

Networks (circuits)
Reverse engineering
Integrated circuits
Hardware
Costs

Keywords

  • Equivalence checker
  • IP piracy
  • Reverse engineering
  • Reversible circuits
  • Stripped functionality logic locking

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering
  • Software

Cite this

Limaye, N., Yasin, M., & Sinanoglu, O. (2019). Revisiting logic locking for reversible computing. In Proceedings - 2019 IEEE European Test Symposium, ETS 2019 [8791550] (Proceedings of the European Test Workshop; Vol. 2019-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ETS.2019.8791550

Revisiting logic locking for reversible computing. / Limaye, Nimisha; Yasin, Muhammad; Sinanoglu, Ozgur.

Proceedings - 2019 IEEE European Test Symposium, ETS 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8791550 (Proceedings of the European Test Workshop; Vol. 2019-May).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Limaye, N, Yasin, M & Sinanoglu, O 2019, Revisiting logic locking for reversible computing. in Proceedings - 2019 IEEE European Test Symposium, ETS 2019., 8791550, Proceedings of the European Test Workshop, vol. 2019-May, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE European Test Symposium, ETS 2019, Baden-Baden, Germany, 5/27/19. https://doi.org/10.1109/ETS.2019.8791550
Limaye N, Yasin M, Sinanoglu O. Revisiting logic locking for reversible computing. In Proceedings - 2019 IEEE European Test Symposium, ETS 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8791550. (Proceedings of the European Test Workshop). https://doi.org/10.1109/ETS.2019.8791550
Limaye, Nimisha ; Yasin, Muhammad ; Sinanoglu, Ozgur. / Revisiting logic locking for reversible computing. Proceedings - 2019 IEEE European Test Symposium, ETS 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (Proceedings of the European Test Workshop).
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