Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip

Jerry Backer, David Hely, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Systems-on-chip (SoCs) are vulnerable to attacks by malicious software and hardware trojans. This work explores if the Design for Test (DfT) infrastructure in SoCs can tackle these security threats with minimum hardware overhead. We show that the observability and plug-and-play features of the IEEE 1500 DfT can be used for scalable security monitoring in SoCs. Existing SoC security countermeasures can reuse the DfT-based security architecture to detect software and hardware attacks. The proposed DfT reuse imposes negligible hardware and performance overheads and doesn't require modifications to the SoC.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages52-56
Number of pages5
ISBN (Print)9781479961559
DOIs
StatePublished - Nov 18 2014
Event27th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014 - Amsterdam, Netherlands
Duration: Oct 1 2014Oct 3 2014

Other

Other27th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014
CountryNetherlands
CityAmsterdam
Period10/1/1410/3/14

Fingerprint

Monitoring
Hardware
Observability
Computer hardware
System-on-chip
Malware

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Backer, J., Hely, D., & Karri, R. (2014). Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip. In Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (pp. 52-56). [6962098] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFT.2014.6962098

Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip. / Backer, Jerry; Hely, David; Karri, Ramesh.

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Institute of Electrical and Electronics Engineers Inc., 2014. p. 52-56 6962098.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Backer, J, Hely, D & Karri, R 2014, Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip. in Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems., 6962098, Institute of Electrical and Electronics Engineers Inc., pp. 52-56, 27th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014, Amsterdam, Netherlands, 10/1/14. https://doi.org/10.1109/DFT.2014.6962098
Backer J, Hely D, Karri R. Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip. In Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Institute of Electrical and Electronics Engineers Inc. 2014. p. 52-56. 6962098 https://doi.org/10.1109/DFT.2014.6962098
Backer, Jerry ; Hely, David ; Karri, Ramesh. / Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 52-56
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