Reliable computing with ultra-reduced instruction set coprocessors

Dan Wang, Aravindkumar Rajendiran, Sundaram Ananthanarayanan, Hiren Patel, Mahesh V. Tripunitara, Siddharth Garg

Research output: Contribution to journalArticle

Abstract

This work presents a method to reliably perform computations in the presence of hard faults and design defects, based on the observation that a single turing-complete instruction can mirror any other instruction's semantics. the authors extend a mips processor with the ULtra-REduced INstruction SEt Coprocessor (URISC). They evaluate the impact of single-upset faults on the instructions that are rendered faulty and the area and performance overhead of using a URISC.

Original languageEnglish (US)
Article number06679035
Pages (from-to)86-94
Number of pages9
JournalIEEE Micro
Volume34
Issue number6
DOIs
StatePublished - Nov 1 2014

Fingerprint

Mirrors
Semantics
Defects
Coprocessor

Keywords

  • Benchmark testing
  • Decoding
  • Hard faults
  • Instruction sets
  • Microprocessor reliability
  • Multicore processing
  • Network reliability
  • Registers
  • Semantics
  • Turing-complete ISA
  • Ultra-reduced instruction set coprocessor
  • URISC

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Software

Cite this

Wang, D., Rajendiran, A., Ananthanarayanan, S., Patel, H., Tripunitara, M. V., & Garg, S. (2014). Reliable computing with ultra-reduced instruction set coprocessors. IEEE Micro, 34(6), 86-94. [06679035]. https://doi.org/10.1109/MM.2013.130

Reliable computing with ultra-reduced instruction set coprocessors. / Wang, Dan; Rajendiran, Aravindkumar; Ananthanarayanan, Sundaram; Patel, Hiren; Tripunitara, Mahesh V.; Garg, Siddharth.

In: IEEE Micro, Vol. 34, No. 6, 06679035, 01.11.2014, p. 86-94.

Research output: Contribution to journalArticle

Wang, D, Rajendiran, A, Ananthanarayanan, S, Patel, H, Tripunitara, MV & Garg, S 2014, 'Reliable computing with ultra-reduced instruction set coprocessors', IEEE Micro, vol. 34, no. 6, 06679035, pp. 86-94. https://doi.org/10.1109/MM.2013.130
Wang D, Rajendiran A, Ananthanarayanan S, Patel H, Tripunitara MV, Garg S. Reliable computing with ultra-reduced instruction set coprocessors. IEEE Micro. 2014 Nov 1;34(6):86-94. 06679035. https://doi.org/10.1109/MM.2013.130
Wang, Dan ; Rajendiran, Aravindkumar ; Ananthanarayanan, Sundaram ; Patel, Hiren ; Tripunitara, Mahesh V. ; Garg, Siddharth. / Reliable computing with ultra-reduced instruction set coprocessors. In: IEEE Micro. 2014 ; Vol. 34, No. 6. pp. 86-94.
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