Reliable computing with ultra-reduced instruction set co-processors

Aravindkumar Rajendiran, Sundaram Ananthanarayanan, Hiren D. Patel, Mahesh V. Tripunitara, Siddharth Garg

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This work presents a method to reliably perform computations in the presence of hard faults arising from aggressive technology scaling, and design defects from human error. Our method is based on an observation that a single Turing-complete instruction can mirror the semantics of any other instruction. One such instruction is the subleq instruction, which has been used for instructional purposes in the past. We find that the scope for using such a Turing-complete instruction is far greater, and in this paper, we present its applicability to fault tolerance. In particular, we extend a MIPS processor with a co-processor (called ultra-reduced instruction set co-processor - URISC) that implements the subleq instruction. We use the URISC to execute sequences of subleq that are semantically equivalent to the faulty instructions. We formally prove this, and implement the translations in the back-end of the LLVM compiler. We generate binaries for our hardware prototype called MIPS-URISC, which we synthesize and execute on an Altera FPGA. Our experiments indicate the performance and area overheads, and the efficacy of the proposed approach.

Original languageEnglish (US)
Title of host publicationProceedings of the 49th Annual Design Automation Conference, DAC '12
Pages697-702
Number of pages6
DOIs
StatePublished - 2012
Event49th Annual Design Automation Conference, DAC '12 - San Francisco, CA, United States
Duration: Jun 3 2012Jun 7 2012

Other

Other49th Annual Design Automation Conference, DAC '12
CountryUnited States
CitySan Francisco, CA
Period6/3/126/7/12

Fingerprint

Turing
Human Error
Computing
Fault tolerance
Fault Tolerance
Compiler
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Efficacy
Mirror
Mirrors
Fault
Defects
Semantics
Hardware
Scaling
Prototype
Binary
Experiment
Experiments

Keywords

  • microprocessor reliability
  • Turing-complete ISA

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

Cite this

Rajendiran, A., Ananthanarayanan, S., Patel, H. D., Tripunitara, M. V., & Garg, S. (2012). Reliable computing with ultra-reduced instruction set co-processors. In Proceedings of the 49th Annual Design Automation Conference, DAC '12 (pp. 697-702) https://doi.org/10.1145/2228360.2228485

Reliable computing with ultra-reduced instruction set co-processors. / Rajendiran, Aravindkumar; Ananthanarayanan, Sundaram; Patel, Hiren D.; Tripunitara, Mahesh V.; Garg, Siddharth.

Proceedings of the 49th Annual Design Automation Conference, DAC '12. 2012. p. 697-702.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rajendiran, A, Ananthanarayanan, S, Patel, HD, Tripunitara, MV & Garg, S 2012, Reliable computing with ultra-reduced instruction set co-processors. in Proceedings of the 49th Annual Design Automation Conference, DAC '12. pp. 697-702, 49th Annual Design Automation Conference, DAC '12, San Francisco, CA, United States, 6/3/12. https://doi.org/10.1145/2228360.2228485
Rajendiran A, Ananthanarayanan S, Patel HD, Tripunitara MV, Garg S. Reliable computing with ultra-reduced instruction set co-processors. In Proceedings of the 49th Annual Design Automation Conference, DAC '12. 2012. p. 697-702 https://doi.org/10.1145/2228360.2228485
Rajendiran, Aravindkumar ; Ananthanarayanan, Sundaram ; Patel, Hiren D. ; Tripunitara, Mahesh V. ; Garg, Siddharth. / Reliable computing with ultra-reduced instruction set co-processors. Proceedings of the 49th Annual Design Automation Conference, DAC '12. 2012. pp. 697-702
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