Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis

Kaijie Wu, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A fault-secure datapath either generates a correct result or signals an error. This paper presents a register transfer level Concurrent Error Detection (CED) technique that uses hybrid time and hardware redundancy to optimize the time and area overhead associated with fault security. The proposed technique combines the idle computation cycles in a datapath with selective breaking of data dependences of the normal computation. Designers can trade-off time and hardware overhead by varying these design parameters. We present an algorithm to synthesize fault secure designs and validate it using Synopsys Behavioral Compiler.

Original languageEnglish (US)
Title of host publicationIEEE International Test Conference (TC)
Pages902-911
Number of pages10
Publication statusPublished - 2003
EventProceedings International Test Conference 2003 - Charlotte, NC, United States
Duration: Sep 30 2003Oct 2 2003

Other

OtherProceedings International Test Conference 2003
CountryUnited States
CityCharlotte, NC
Period9/30/0310/2/03

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering
  • Hardware and Architecture

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