Reducing average and peak test power through scan chain modification

Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu

Research output: Contribution to journalArticle

Abstract

Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. The transitions embedded in both test stimuli and the responses are handled through scan chain modifications consisting of logic gate insertion between scan cells as well as inversion of capture paths. No performance degradation ensues as these modifications have no impact on functional execution. To reduce average and peak power, we herein propose computationally efficient schemes that identify the location and the type of logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.

Original languageEnglish (US)
Pages (from-to)457-467
Number of pages11
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Volume19
Issue number4
DOIs
StatePublished - Aug 1 2003

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Switching circuits
Logic gates
Degradation

Keywords

  • Average test power
  • Peak test power
  • Scan chain modification
  • Scan testing
  • Test power reduction

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Reducing average and peak test power through scan chain modification. / Sinanoglu, Ozgur; Bayraktaroglu, Ismet; Orailoglu, Alex.

In: Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 19, No. 4, 01.08.2003, p. 457-467.

Research output: Contribution to journalArticle

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