Reducing average and peak test power through scan chain modification

Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu

    Research output: Contribution to journalArticle

    Abstract

    Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. The transitions embedded in both test stimuli and the responses are handled through scan chain modifications consisting of logic gate insertion between scan cells as well as inversion of capture paths. No performance degradation ensues as these modifications have no impact on functional execution. To reduce average and peak power, we herein propose computationally efficient schemes that identify the location and the type of logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.

    Original languageEnglish (US)
    Pages (from-to)457-467
    Number of pages11
    JournalJournal of Electronic Testing: Theory and Applications (JETTA)
    Volume19
    Issue number4
    DOIs
    StatePublished - Aug 1 2003

    Fingerprint

    Switching circuits
    Logic gates
    Degradation

    Keywords

    • Average test power
    • Peak test power
    • Scan chain modification
    • Scan testing
    • Test power reduction

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Reducing average and peak test power through scan chain modification. / Sinanoglu, Ozgur; Bayraktaroglu, Ismet; Orailoglu, Alex.

    In: Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 19, No. 4, 01.08.2003, p. 457-467.

    Research output: Contribution to journalArticle

    Sinanoglu, Ozgur ; Bayraktaroglu, Ismet ; Orailoglu, Alex. / Reducing average and peak test power through scan chain modification. In: Journal of Electronic Testing: Theory and Applications (JETTA). 2003 ; Vol. 19, No. 4. pp. 457-467.
    @article{18a4a76f5a3a418fb71950b07fe9474b,
    title = "Reducing average and peak test power through scan chain modification",
    abstract = "Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. The transitions embedded in both test stimuli and the responses are handled through scan chain modifications consisting of logic gate insertion between scan cells as well as inversion of capture paths. No performance degradation ensues as these modifications have no impact on functional execution. To reduce average and peak power, we herein propose computationally efficient schemes that identify the location and the type of logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.",
    keywords = "Average test power, Peak test power, Scan chain modification, Scan testing, Test power reduction",
    author = "Ozgur Sinanoglu and Ismet Bayraktaroglu and Alex Orailoglu",
    year = "2003",
    month = "8",
    day = "1",
    doi = "10.1023/A:1024600311740",
    language = "English (US)",
    volume = "19",
    pages = "457--467",
    journal = "Journal of Electronic Testing: Theory and Applications (JETTA)",
    issn = "0923-8174",
    publisher = "Springer Netherlands",
    number = "4",

    }

    TY - JOUR

    T1 - Reducing average and peak test power through scan chain modification

    AU - Sinanoglu, Ozgur

    AU - Bayraktaroglu, Ismet

    AU - Orailoglu, Alex

    PY - 2003/8/1

    Y1 - 2003/8/1

    N2 - Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. The transitions embedded in both test stimuli and the responses are handled through scan chain modifications consisting of logic gate insertion between scan cells as well as inversion of capture paths. No performance degradation ensues as these modifications have no impact on functional execution. To reduce average and peak power, we herein propose computationally efficient schemes that identify the location and the type of logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.

    AB - Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. The transitions embedded in both test stimuli and the responses are handled through scan chain modifications consisting of logic gate insertion between scan cells as well as inversion of capture paths. No performance degradation ensues as these modifications have no impact on functional execution. To reduce average and peak power, we herein propose computationally efficient schemes that identify the location and the type of logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.

    KW - Average test power

    KW - Peak test power

    KW - Scan chain modification

    KW - Scan testing

    KW - Test power reduction

    UR - http://www.scopus.com/inward/record.url?scp=0041473850&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=0041473850&partnerID=8YFLogxK

    U2 - 10.1023/A:1024600311740

    DO - 10.1023/A:1024600311740

    M3 - Article

    VL - 19

    SP - 457

    EP - 467

    JO - Journal of Electronic Testing: Theory and Applications (JETTA)

    JF - Journal of Electronic Testing: Theory and Applications (JETTA)

    SN - 0923-8174

    IS - 4

    ER -