Reconfigurable low-power Concurrent Error Detection in logic circuits

Sobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Concurrent Error Detection (CED) methods provide some level of error detection capability at the cost of some area and power overhead. In many portable devices, however, the error detection capability must be reconfigured dynamically, in order to optimize the available power budget according to the criticality of the processed data. In this work, we propose a reconfigurable duplication-based CED infrastructure for logic circuits. The key idea is to enable/disable the operation of the duplicate circuit according to a set of control conditions. When CED is disabled, the inputs to the duplicate circuit retain their previous values (i.e., reduction in power dissipation via elimination of switching activity), yet errors are not detected (i.e., reduction in CED coverage). Experimental results using judicious and random selection of control conditions yield the same end-result; power dissipation is commensurate with CED coverage. Therefore, LFSR structures can be used to easily generate and reconfigure conditions, enabling their dynamic adjustment to adapt to the power constraints of the system.

Original languageEnglish (US)
Title of host publicationProceedings of the 2010 IEEE 16th International On-Line Testing Symposium, IOLTS 2010
Pages206-207
Number of pages2
DOIs
StatePublished - Oct 22 2010
Event16th IEEE International On-Line Testing Symposium, IOLTS 2010 - Corfu Island, Greece
Duration: Jul 5 2010Jul 7 2010

Other

Other16th IEEE International On-Line Testing Symposium, IOLTS 2010
CountryGreece
CityCorfu Island
Period7/5/107/7/10

Fingerprint

Logic circuits
Error detection
Energy dissipation
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Almukhaizim, S., Bunian, S., & Sinanoglu, O. (2010). Reconfigurable low-power Concurrent Error Detection in logic circuits. In Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium, IOLTS 2010 (pp. 206-207). [5560202] https://doi.org/10.1109/IOLTS.2010.5560202

Reconfigurable low-power Concurrent Error Detection in logic circuits. / Almukhaizim, Sobeeh; Bunian, Sara; Sinanoglu, Ozgur.

Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium, IOLTS 2010. 2010. p. 206-207 5560202.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Almukhaizim, S, Bunian, S & Sinanoglu, O 2010, Reconfigurable low-power Concurrent Error Detection in logic circuits. in Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium, IOLTS 2010., 5560202, pp. 206-207, 16th IEEE International On-Line Testing Symposium, IOLTS 2010, Corfu Island, Greece, 7/5/10. https://doi.org/10.1109/IOLTS.2010.5560202
Almukhaizim S, Bunian S, Sinanoglu O. Reconfigurable low-power Concurrent Error Detection in logic circuits. In Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium, IOLTS 2010. 2010. p. 206-207. 5560202 https://doi.org/10.1109/IOLTS.2010.5560202
Almukhaizim, Sobeeh ; Bunian, Sara ; Sinanoglu, Ozgur. / Reconfigurable low-power Concurrent Error Detection in logic circuits. Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium, IOLTS 2010. 2010. pp. 206-207
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