Reconfigurable low-power concurrent error detection in logic circuits

Sobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Concurrent Error Detection (CED) methods are commonly employed to provide some level of error detection capability at the cost of some area and power overhead. In many applications, however, the error detection capability must be reconfigured dynamically, in order to adapt to the available power budget, criticality of the processed data, a thermal-safe schedule, etc. In this work, we propose a reconfigurable duplication-based CED infrastructure for logic circuits. The key idea is to enable/disable the operation of the duplicate circuit according to a set of control conditions. When CED is disabled, the inputs to the duplicate circuit retain their previous values (i.e., reduction in power dissipation via elimination of switching activity), yet errors are not detected (i.e., reduction in CED coverage). Experimental results using judicious and random selection of control conditions yield the same end-result; power dissipation is commensurate with CED coverage. Therefore, LFSR structures can be used to easily generate and reconfigure conditions, enabling their dynamic adjustment to adapt to the power constraints of the system.

Original languageEnglish (US)
Title of host publicationIDT'10 - 2010 5th International Design and Test Workshop, Proceedings
Pages91-96
Number of pages6
DOIs
StatePublished - Dec 1 2010
Event2010 5th International Design and Test Workshop, IDT'10 - Abu Dhabi, United Arab Emirates
Duration: Dec 14 2010Dec 15 2010

Other

Other2010 5th International Design and Test Workshop, IDT'10
CountryUnited Arab Emirates
CityAbu Dhabi
Period12/14/1012/15/10

Fingerprint

Logic circuits
Error detection
Energy dissipation
Networks (circuits)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Almukhaizim, S., Bunian, S., & Sinanoglu, O. (2010). Reconfigurable low-power concurrent error detection in logic circuits. In IDT'10 - 2010 5th International Design and Test Workshop, Proceedings (pp. 91-96). [5724415] https://doi.org/10.1109/IDT.2010.5724415

Reconfigurable low-power concurrent error detection in logic circuits. / Almukhaizim, Sobeeh; Bunian, Sara; Sinanoglu, Ozgur.

IDT'10 - 2010 5th International Design and Test Workshop, Proceedings. 2010. p. 91-96 5724415.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Almukhaizim, S, Bunian, S & Sinanoglu, O 2010, Reconfigurable low-power concurrent error detection in logic circuits. in IDT'10 - 2010 5th International Design and Test Workshop, Proceedings., 5724415, pp. 91-96, 2010 5th International Design and Test Workshop, IDT'10, Abu Dhabi, United Arab Emirates, 12/14/10. https://doi.org/10.1109/IDT.2010.5724415
Almukhaizim S, Bunian S, Sinanoglu O. Reconfigurable low-power concurrent error detection in logic circuits. In IDT'10 - 2010 5th International Design and Test Workshop, Proceedings. 2010. p. 91-96. 5724415 https://doi.org/10.1109/IDT.2010.5724415
Almukhaizim, Sobeeh ; Bunian, Sara ; Sinanoglu, Ozgur. / Reconfigurable low-power concurrent error detection in logic circuits. IDT'10 - 2010 5th International Design and Test Workshop, Proceedings. 2010. pp. 91-96
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