Process-driven variability analysis of single and multiple voltage-frequency island latency-constrained systems

Diana Marculescu, Siddharth Garg

Research output: Contribution to journalArticle

Abstract

The problem of determining bounds for application completion times running on generic systems comprising single or multiple voltagefrequency islands (VFIs) with arbitrary topologies is addressed in the context of manufacturing-process- driven variability. The approach provides an exact solution for the system-level timing yield in synchronous single-voltage (SSV) and VFI systems with an underlying tree-based topology and a tight upper bound for generic non-tree-based topologies. The results show that: 1) timing yield for the overall source-to-sink completion time for generic systems can be modeled in an exact manner for both SSV and VFI systems and 2) multiple-VFI latency-constrained systems can achieve up to two times higher timing yield than their SSV counterparts. The results are formally proven and are supported by experimental results on two embedded applications, namely, a software-defined radio and a Moving Pictures Expert Group 2 encoder.

Original languageEnglish (US)
Article number4492838
Pages (from-to)893-904
Number of pages12
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume27
Issue number5
DOIs
StatePublished - May 2008

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Topology
Electric potential

Keywords

  • Design variability
  • Performance analysis
  • Voltage-frequency islands

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Computer Science Applications
  • Computational Theory and Mathematics

Cite this

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abstract = "The problem of determining bounds for application completion times running on generic systems comprising single or multiple voltagefrequency islands (VFIs) with arbitrary topologies is addressed in the context of manufacturing-process- driven variability. The approach provides an exact solution for the system-level timing yield in synchronous single-voltage (SSV) and VFI systems with an underlying tree-based topology and a tight upper bound for generic non-tree-based topologies. The results show that: 1) timing yield for the overall source-to-sink completion time for generic systems can be modeled in an exact manner for both SSV and VFI systems and 2) multiple-VFI latency-constrained systems can achieve up to two times higher timing yield than their SSV counterparts. The results are formally proven and are supported by experimental results on two embedded applications, namely, a software-defined radio and a Moving Pictures Expert Group 2 encoder.",
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