### Abstract

We present an architecture level low power design technique called divide-and-concatenate for universal hash functions based on the following observations: (i) the power consumption of a w-bit array multiplier and associated universal hash data path decreases as O(w^{4}) if its clock rate remains constant, (ii) two universal hash functions are equivalent if they have the same collision probability property. In the proposed approach we divide a w-bit data path (with collision probability 2^{-w}) into two/four w/2-bit data paths (each with collision probability 2^{-w/2}) and concatenate their results to construct an equivalent w-bit data path (with a collision probability 2^{-w}). A popular low power technique that uses parallel data paths saves 62.10% dynamic power consumption incurring 102% area overhead. In contrast, the divide-and-concatenate technique saves 55.44% dynamic power consumption with only 16% area overhead.

Original language | English (US) |
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Title of host publication | CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and Systems Synthesis |

Pages | 219-224 |

Number of pages | 6 |

State | Published - 2005 |

Event | 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis CODES+ISSS 2005 - Jersey City, NJ, United States Duration: Sep 18 2005 → Sep 21 2005 |

### Other

Other | 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis CODES+ISSS 2005 |
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Country | United States |

City | Jersey City, NJ |

Period | 9/18/05 → 9/21/05 |

### Fingerprint

### Keywords

- Divide-and-Concatenate
- Power Optimization
- Universal Hash Function

### ASJC Scopus subject areas

- Engineering(all)

### Cite this

*CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and Systems Synthesis*(pp. 219-224)

**Power optimization for universal hash function data path using divide-and-concatenate technique.** / Yang, Bo; Karri, Ramesh.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

*CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and Systems Synthesis.*pp. 219-224, 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis CODES+ISSS 2005, Jersey City, NJ, United States, 9/18/05.

}

TY - GEN

T1 - Power optimization for universal hash function data path using divide-and-concatenate technique

AU - Yang, Bo

AU - Karri, Ramesh

PY - 2005

Y1 - 2005

N2 - We present an architecture level low power design technique called divide-and-concatenate for universal hash functions based on the following observations: (i) the power consumption of a w-bit array multiplier and associated universal hash data path decreases as O(w4) if its clock rate remains constant, (ii) two universal hash functions are equivalent if they have the same collision probability property. In the proposed approach we divide a w-bit data path (with collision probability 2-w) into two/four w/2-bit data paths (each with collision probability 2-w/2) and concatenate their results to construct an equivalent w-bit data path (with a collision probability 2-w). A popular low power technique that uses parallel data paths saves 62.10% dynamic power consumption incurring 102% area overhead. In contrast, the divide-and-concatenate technique saves 55.44% dynamic power consumption with only 16% area overhead.

AB - We present an architecture level low power design technique called divide-and-concatenate for universal hash functions based on the following observations: (i) the power consumption of a w-bit array multiplier and associated universal hash data path decreases as O(w4) if its clock rate remains constant, (ii) two universal hash functions are equivalent if they have the same collision probability property. In the proposed approach we divide a w-bit data path (with collision probability 2-w) into two/four w/2-bit data paths (each with collision probability 2-w/2) and concatenate their results to construct an equivalent w-bit data path (with a collision probability 2-w). A popular low power technique that uses parallel data paths saves 62.10% dynamic power consumption incurring 102% area overhead. In contrast, the divide-and-concatenate technique saves 55.44% dynamic power consumption with only 16% area overhead.

KW - Divide-and-Concatenate

KW - Power Optimization

KW - Universal Hash Function

UR - http://www.scopus.com/inward/record.url?scp=27644484399&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=27644484399&partnerID=8YFLogxK

M3 - Conference contribution

SN - 1595931619

SP - 219

EP - 224

BT - CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and Systems Synthesis

ER -