Power-aware virtual machine mapping in the data-center-on-a-chip paradigm

Xue Lin, Yuankun Xue, Paul Bogdan, Yanzhi Wang, Siddharth Garg, Massoud Pedram

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

It is projected that hundreds of cores can be integrated into a chip at the sub-20nm technology nodes. However, some challenges exist in the many-core architecture such as maintaining memory coherence, underutilized parallelism, and increased inter-core communication delay. This work proposes the data-center-on-a-chip (DCoC) paradigm employing virtualization technologies commonly used in today's data centers to reduce the overhead of maintaining memory coherence and inter-core communication and improve parallelism. In the DCoC paradigm, user applications with specific resource requirements need to be mapped onto different chips of a data center and different cores of a chip in the form of virtual machines (VMs). By a judicious VM mapping method, the data center performance can be maximized while satisfying the power budget and power density constraints of the chips and the resource requirements of VMs. To tackle the NP-hardness of the VM mapping problem, we propose a two-tier algorithm, which effectively solves the mapping problem with polynomial time complexity.

Original languageEnglish (US)
Title of host publicationProceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages241-248
Number of pages8
ISBN (Electronic)9781509051427
DOIs
StatePublished - Nov 22 2016
Event34th IEEE International Conference on Computer Design, ICCD 2016 - Scottsdale, United States
Duration: Oct 2 2016Oct 5 2016

Other

Other34th IEEE International Conference on Computer Design, ICCD 2016
CountryUnited States
CityScottsdale
Period10/2/1610/5/16

Fingerprint

Data storage equipment
Communication
Hardness
Polynomials
Virtual machine
Virtualization

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Lin, X., Xue, Y., Bogdan, P., Wang, Y., Garg, S., & Pedram, M. (2016). Power-aware virtual machine mapping in the data-center-on-a-chip paradigm. In Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016 (pp. 241-248). [7753286] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCD.2016.7753286

Power-aware virtual machine mapping in the data-center-on-a-chip paradigm. / Lin, Xue; Xue, Yuankun; Bogdan, Paul; Wang, Yanzhi; Garg, Siddharth; Pedram, Massoud.

Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 241-248 7753286.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lin, X, Xue, Y, Bogdan, P, Wang, Y, Garg, S & Pedram, M 2016, Power-aware virtual machine mapping in the data-center-on-a-chip paradigm. in Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016., 7753286, Institute of Electrical and Electronics Engineers Inc., pp. 241-248, 34th IEEE International Conference on Computer Design, ICCD 2016, Scottsdale, United States, 10/2/16. https://doi.org/10.1109/ICCD.2016.7753286
Lin X, Xue Y, Bogdan P, Wang Y, Garg S, Pedram M. Power-aware virtual machine mapping in the data-center-on-a-chip paradigm. In Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 241-248. 7753286 https://doi.org/10.1109/ICCD.2016.7753286
Lin, Xue ; Xue, Yuankun ; Bogdan, Paul ; Wang, Yanzhi ; Garg, Siddharth ; Pedram, Massoud. / Power-aware virtual machine mapping in the data-center-on-a-chip paradigm. Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 241-248
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