Polymorphic spintronic logic gates for hardware security primitives-Device design and performance benchmarking

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents polymorphic logic gates for hardware security using giant spin Hall effect (GSHE) devices in which electron spin is the information token. Compared to existing CMOS (charge-based) IP protection and camouflaging security techniques, the proposed GSHE logic offers significant reduction in implementation area as well as power dissipation. Based on the Monte-Carlo simulation of stochastic Landau Lifshitz Gilbert Slonczewski (s-LLGS) equation governing the GSHE dynamics, physical models of delay, energy-per-bit, and power dissipation are developed for GSHE standard cells including inverter, NAND, NOR, and XOR gate. We note that the proposed GSHE polymorphic logic can implement majority function by simply reversing the voltage polarity on the gate terminals. The same layout structure implements complex logic functions by selecting the appropriate polarity of a control signal. As such, it offers post-fabrication reconfigurability options to implement evolvable and intelligent hardware.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages131-132
Number of pages2
ISBN (Electronic)9781509060368
DOIs
StatePublished - Sep 28 2017
Event2017 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017 - Newport, United States
Duration: Jul 25 2017Jul 26 2017

Other

Other2017 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017
CountryUnited States
CityNewport
Period7/25/177/26/17

Fingerprint

Spin Hall effect
Magnetoelectronics
Logic gates
Benchmarking
Energy dissipation
Hall effect devices
Hardware security
Hardware
Fabrication
Electrons
Electric potential

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Networks and Communications

Cite this

Rakheja, S., & Kani, N. (2017). Polymorphic spintronic logic gates for hardware security primitives-Device design and performance benchmarking. In Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017 (pp. 131-132). [8053726] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NANOARCH.2017.8053726

Polymorphic spintronic logic gates for hardware security primitives-Device design and performance benchmarking. / Rakheja, Shaloo; Kani, N.

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 131-132 8053726.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rakheja, S & Kani, N 2017, Polymorphic spintronic logic gates for hardware security primitives-Device design and performance benchmarking. in Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017., 8053726, Institute of Electrical and Electronics Engineers Inc., pp. 131-132, 2017 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017, Newport, United States, 7/25/17. https://doi.org/10.1109/NANOARCH.2017.8053726
Rakheja S, Kani N. Polymorphic spintronic logic gates for hardware security primitives-Device design and performance benchmarking. In Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 131-132. 8053726 https://doi.org/10.1109/NANOARCH.2017.8053726
Rakheja, Shaloo ; Kani, N. / Polymorphic spintronic logic gates for hardware security primitives-Device design and performance benchmarking. Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 131-132
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