Polaris

A system-level roadmapping toolchain for on-chip interconnection networks

Vassos Soteriou Soteriou, Noel Eisley, Hangsheng Wang, Bin Li, Li Shiuan Peh

    Research output: Contribution to journalArticle

    Abstract

    Technology trends are driving parallel on-chip architectures in the form of multiprocessor systems-on-a-chip (MPSoCs) and chip multiprocessors (CMPs). In these systems, the increasing on-chip communication demand among the computation elements necessitates the use of scalable, high-bandwidth network-on-chip (NoC) fabrics instead of dedicated interconnects and shared buses. As transistor feature sizes are further miniaturized, more complicated NoC architectures become feasible that can support more demanding applications. Given the myriad emerging software-hardware combinations, for cost-effectiveness, a system designer critically needs to prune this widening NoC design-space to predict the interconnect fabric(s) that best balance(s) cost/performance, before the actual design process begins. This prompted us to develop Polaris, a system-level roadmapping toolchain for on-chip interconnection networks that helps designers predict the most suitable interconnection network design(s) tailored to their performance needs and power/silicon area constraints with respect to a range of applications that the system will run. Polaris explores the plethora of NoC designs based on projections of network traffic, architectures, and process characteristics. While Polaris's toolchain is extensible so new traffic, network designs, and technology processes can be added, the current version already incorporates 7872 NoC design points. Polaris is rapid, efficiently iterating over thousands of NoC design points, while maintaining high relative and absolute accuracies when validated against detailed NoC synthesis results.

    Original languageEnglish (US)
    Pages (from-to)855-868
    Number of pages14
    JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
    Volume15
    Issue number8
    DOIs
    StatePublished - Aug 1 2007

    Fingerprint

    Cost effectiveness
    Network-on-chip
    Transistors
    Hardware
    Bandwidth
    Silicon
    Communication
    Costs

    Keywords

    • Interconnection networks, networks-on-chip (NoCs)
    • Roadmap
    • Simulation
    • Software tools

    ASJC Scopus subject areas

    • Software
    • Hardware and Architecture
    • Electrical and Electronic Engineering

    Cite this

    Polaris : A system-level roadmapping toolchain for on-chip interconnection networks. / Soteriou, Vassos Soteriou; Eisley, Noel; Wang, Hangsheng; Li, Bin; Peh, Li Shiuan.

    In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 15, No. 8, 01.08.2007, p. 855-868.

    Research output: Contribution to journalArticle

    Soteriou, Vassos Soteriou ; Eisley, Noel ; Wang, Hangsheng ; Li, Bin ; Peh, Li Shiuan. / Polaris : A system-level roadmapping toolchain for on-chip interconnection networks. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2007 ; Vol. 15, No. 8. pp. 855-868.
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