Polaris

A system-level roadmap for on-chip interconnection networks

Vassos Soteriou Soteriou, Noel Eisley, Hangsheng Wang, Bin Li, Li Shiuan Peh

    Research output: Contribution to conferencePaper

    Abstract

    Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the increasing on-chip communication demand among the computation elements necessitates the use of scalable, nigh-bandwidth network-on-chip (NoC) fabrics. As transistor feature sizes are further miniaturized leading to rapidly increasing amounts of on-chip resources, more complicated and powerful NoC architectures become feasible that can support more sophisticated and demanding applications. Given tne myriad emerging software-hardware combinations, for cost-effectiveness, a system designer critically needs to prune this widening NoC design space to identify the architecture(s) that best balance(s) cost/performance, before the actual design process begins. This prompted us to develop Polaris1, a system-level roadmap for onchip interconnection networks that guides designers towards the most suitable network design(s) tailored to their performance needs and power/silicon area constraints with respect to a range of applications that will run over this network(s). Polaris explores tne plethora of NoC designs based on projections of network traffic, architectures, and process characteristics. While the Polaris roadmapping toolchain is extensible so new traffic, network designs, and processes can be added, the current version of the roadmap already incorporates 7,872 NoC design points. Polaris is rapid and iterates over all these NoC architectures within a tractable run time of 125 hours on a typical desktop machine, while maintaining high relative and absolute accuracies when validated against detailed NoC synthesis results.

    Original languageEnglish (US)
    Pages134-141
    Number of pages8
    DOIs
    StatePublished - Dec 1 2006
    Event24th International Conference on Computer Design 2006, ICCD - San Jose, CA, United States
    Duration: Oct 1 2006Oct 4 2006

    Other

    Other24th International Conference on Computer Design 2006, ICCD
    CountryUnited States
    CitySan Jose, CA
    Period10/1/0610/4/06

    Fingerprint

    Cost effectiveness
    Network-on-chip
    Transistors
    Hardware
    Bandwidth
    Silicon
    Communication
    Costs

    ASJC Scopus subject areas

    • Computer Graphics and Computer-Aided Design
    • Software

    Cite this

    Soteriou, V. S., Eisley, N., Wang, H., Li, B., & Peh, L. S. (2006). Polaris: A system-level roadmap for on-chip interconnection networks. 134-141. Paper presented at 24th International Conference on Computer Design 2006, ICCD, San Jose, CA, United States. https://doi.org/10.1109/ICCD.2006.4380806

    Polaris : A system-level roadmap for on-chip interconnection networks. / Soteriou, Vassos Soteriou; Eisley, Noel; Wang, Hangsheng; Li, Bin; Peh, Li Shiuan.

    2006. 134-141 Paper presented at 24th International Conference on Computer Design 2006, ICCD, San Jose, CA, United States.

    Research output: Contribution to conferencePaper

    Soteriou, VS, Eisley, N, Wang, H, Li, B & Peh, LS 2006, 'Polaris: A system-level roadmap for on-chip interconnection networks' Paper presented at 24th International Conference on Computer Design 2006, ICCD, San Jose, CA, United States, 10/1/06 - 10/4/06, pp. 134-141. https://doi.org/10.1109/ICCD.2006.4380806
    Soteriou VS, Eisley N, Wang H, Li B, Peh LS. Polaris: A system-level roadmap for on-chip interconnection networks. 2006. Paper presented at 24th International Conference on Computer Design 2006, ICCD, San Jose, CA, United States. https://doi.org/10.1109/ICCD.2006.4380806
    Soteriou, Vassos Soteriou ; Eisley, Noel ; Wang, Hangsheng ; Li, Bin ; Peh, Li Shiuan. / Polaris : A system-level roadmap for on-chip interconnection networks. Paper presented at 24th International Conference on Computer Design 2006, ICCD, San Jose, CA, United States.8 p.
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