Physical limitations on delay and energy dissipation of interconnects for post-CMOS devices

Shaloo Rakheja, Azad Naeemi, James D. Meindl

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In order to maintain the historical scaling of computational power in information processing beyond the 2020 technology node, switches that are based on state variables other than electron charge are currently being investigated. Examples of alternate state variables include the electron spin, pseudo-spin in graphene, and excitons. This paper discusses different communication mechanisms for on-chip local interconnects for post-CMOS devices. Models for delay and energy dissipation for novel interconnects are obtained, and a comparison is provided with their CMOS counterpart. It is shown that novel interconnects can potentially consume less energy per bit as compared to the CMOS interconnects. However, they pose significant delay penalty. The paper highlights some of the major implications of the novel interconnects on the post-CMOS circuits.

Original languageEnglish (US)
Title of host publication2010 IEEE International Interconnect Technology Conference, IITC 2010
DOIs
StatePublished - 2010
Event2010 IEEE International Interconnect Technology Conference, IITC 2010 - Burlingame, CA, United States
Duration: Jun 6 2010Jun 9 2010

Other

Other2010 IEEE International Interconnect Technology Conference, IITC 2010
CountryUnited States
CityBurlingame, CA
Period6/6/106/9/10

Fingerprint

Energy dissipation
Electrons
Excitons
Graphene
Switches
Networks (circuits)
Communication

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture

Cite this

Rakheja, S., Naeemi, A., & Meindl, J. D. (2010). Physical limitations on delay and energy dissipation of interconnects for post-CMOS devices. In 2010 IEEE International Interconnect Technology Conference, IITC 2010 [5510448] https://doi.org/10.1109/IITC.2010.5510448

Physical limitations on delay and energy dissipation of interconnects for post-CMOS devices. / Rakheja, Shaloo; Naeemi, Azad; Meindl, James D.

2010 IEEE International Interconnect Technology Conference, IITC 2010. 2010. 5510448.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rakheja, S, Naeemi, A & Meindl, JD 2010, Physical limitations on delay and energy dissipation of interconnects for post-CMOS devices. in 2010 IEEE International Interconnect Technology Conference, IITC 2010., 5510448, 2010 IEEE International Interconnect Technology Conference, IITC 2010, Burlingame, CA, United States, 6/6/10. https://doi.org/10.1109/IITC.2010.5510448
Rakheja S, Naeemi A, Meindl JD. Physical limitations on delay and energy dissipation of interconnects for post-CMOS devices. In 2010 IEEE International Interconnect Technology Conference, IITC 2010. 2010. 5510448 https://doi.org/10.1109/IITC.2010.5510448
Rakheja, Shaloo ; Naeemi, Azad ; Meindl, James D. / Physical limitations on delay and energy dissipation of interconnects for post-CMOS devices. 2010 IEEE International Interconnect Technology Conference, IITC 2010. 2010.
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