Performance modeling for interconnects for conventional and emerging switches

Shaloo Rakheja, Vachan Kumar, Azad Naeemi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper quantifies the challenges, limits, and opportunities of interconnects for evolutionary and revolutionary semiconductor technologies of the future. Various exploratory devices and the delays associated with their transport mechanisms are quantified. Graphene is selected as the interconnect material of choice because of its excellent transport properties over the conventional Cu/low-K: interconnects currently serving as the communication medium in integrated circuits. Compact models that describe the transport properties in graphene (electron mean free path, mobility, spin relaxation) are presented. These compact models are used to (i) evaluate the performance and energy-per-bit of graphene interconnects in electrical and spintronic domains and (ii) compare these metrics against those of conventional electrical interconnects at the end of silicon roadmap technology node (minimum feature size of 7.5 nm).

Original languageEnglish (US)
Title of host publication2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013
PublisherAssociation for Computing Machinery
ISBN (Print)9781467361736
DOIs
StatePublished - 2013
Event2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013 - Austin, TX, United States
Duration: Jun 2 2013Jun 2 2013

Other

Other2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013
CountryUnited States
CityAustin, TX
Period6/2/136/2/13

Fingerprint

Performance Modeling
Interconnect
Graphene
Switch
Switches
Electron transport properties
Transport Properties
Magnetoelectronics
Transport properties
Integrated circuits
Spintronics
Semiconductor materials
Silicon
Integrated Circuits
Electrons
Communication
Semiconductors
Quantify
Electron
Metric

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Applied Mathematics

Cite this

Rakheja, S., Kumar, V., & Naeemi, A. (2013). Performance modeling for interconnects for conventional and emerging switches. In 2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013 [6681683] Association for Computing Machinery. https://doi.org/10.1109/SLIP.2013.6681683

Performance modeling for interconnects for conventional and emerging switches. / Rakheja, Shaloo; Kumar, Vachan; Naeemi, Azad.

2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013. Association for Computing Machinery, 2013. 6681683.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rakheja, S, Kumar, V & Naeemi, A 2013, Performance modeling for interconnects for conventional and emerging switches. in 2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013., 6681683, Association for Computing Machinery, 2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013, Austin, TX, United States, 6/2/13. https://doi.org/10.1109/SLIP.2013.6681683
Rakheja S, Kumar V, Naeemi A. Performance modeling for interconnects for conventional and emerging switches. In 2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013. Association for Computing Machinery. 2013. 6681683 https://doi.org/10.1109/SLIP.2013.6681683
Rakheja, Shaloo ; Kumar, Vachan ; Naeemi, Azad. / Performance modeling for interconnects for conventional and emerging switches. 2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013. Association for Computing Machinery, 2013.
@inproceedings{88e9163445404242809e1d0419627e61,
title = "Performance modeling for interconnects for conventional and emerging switches",
abstract = "This paper quantifies the challenges, limits, and opportunities of interconnects for evolutionary and revolutionary semiconductor technologies of the future. Various exploratory devices and the delays associated with their transport mechanisms are quantified. Graphene is selected as the interconnect material of choice because of its excellent transport properties over the conventional Cu/low-K: interconnects currently serving as the communication medium in integrated circuits. Compact models that describe the transport properties in graphene (electron mean free path, mobility, spin relaxation) are presented. These compact models are used to (i) evaluate the performance and energy-per-bit of graphene interconnects in electrical and spintronic domains and (ii) compare these metrics against those of conventional electrical interconnects at the end of silicon roadmap technology node (minimum feature size of 7.5 nm).",
author = "Shaloo Rakheja and Vachan Kumar and Azad Naeemi",
year = "2013",
doi = "10.1109/SLIP.2013.6681683",
language = "English (US)",
isbn = "9781467361736",
booktitle = "2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013",
publisher = "Association for Computing Machinery",

}

TY - GEN

T1 - Performance modeling for interconnects for conventional and emerging switches

AU - Rakheja, Shaloo

AU - Kumar, Vachan

AU - Naeemi, Azad

PY - 2013

Y1 - 2013

N2 - This paper quantifies the challenges, limits, and opportunities of interconnects for evolutionary and revolutionary semiconductor technologies of the future. Various exploratory devices and the delays associated with their transport mechanisms are quantified. Graphene is selected as the interconnect material of choice because of its excellent transport properties over the conventional Cu/low-K: interconnects currently serving as the communication medium in integrated circuits. Compact models that describe the transport properties in graphene (electron mean free path, mobility, spin relaxation) are presented. These compact models are used to (i) evaluate the performance and energy-per-bit of graphene interconnects in electrical and spintronic domains and (ii) compare these metrics against those of conventional electrical interconnects at the end of silicon roadmap technology node (minimum feature size of 7.5 nm).

AB - This paper quantifies the challenges, limits, and opportunities of interconnects for evolutionary and revolutionary semiconductor technologies of the future. Various exploratory devices and the delays associated with their transport mechanisms are quantified. Graphene is selected as the interconnect material of choice because of its excellent transport properties over the conventional Cu/low-K: interconnects currently serving as the communication medium in integrated circuits. Compact models that describe the transport properties in graphene (electron mean free path, mobility, spin relaxation) are presented. These compact models are used to (i) evaluate the performance and energy-per-bit of graphene interconnects in electrical and spintronic domains and (ii) compare these metrics against those of conventional electrical interconnects at the end of silicon roadmap technology node (minimum feature size of 7.5 nm).

UR - http://www.scopus.com/inward/record.url?scp=84893353567&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84893353567&partnerID=8YFLogxK

U2 - 10.1109/SLIP.2013.6681683

DO - 10.1109/SLIP.2013.6681683

M3 - Conference contribution

AN - SCOPUS:84893353567

SN - 9781467361736

BT - 2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013

PB - Association for Computing Machinery

ER -