Performance evaluation of copper and graphene nanoribbons in 2-D NoC structures

Ruturaj Pujari, Shaloo Rakheja

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, performance models of different network-on-chip (NoC) topologies are developed by a) incorporating physical models of the interconnect structures, and b) specifying the microarchitecture of cores and on-chip routers at 15 nm technology node for a clock frequency of 4 GHz. By incorporating device and interconnect models, we implement a cross-layer design and optimization of the performance of NoC architectures. The performance modeling is carried out for mesh, torus, and flattened butterfly (FBFLY) NoC topologies by focusing on global copper (Cu/low-κ) and graphene nanoribbons (GNRs) as the interconnect infrastructure for inter-core communication. The findings show that mesh NoCs incorporated with Cu/low-κ or GNRs have the same latency metrics, while for torus and FBFLY NoCs, the high latency of GNR interconnects is prohibitive. Mesh, torus, and FBFLY topologies with GNRs as inter-core interconnects result in lower interconnect energy dissipation compared to Cu/low-κ interconnects. The worst-case delay for mesh NoCs is equally governed by the on-chip router delay and inter-core interconnects delay but for torus and FBFLY NoCs, delay form inter-core interconnects particularly limits their performance. Therefore, ignoring the interconnect latency in this analysis overestimates the NoC performance significantly. We also determine the optimal network size up to which networks on-chip (NoCs) with GNR interconnects give lower energy-delay product (EDP) when compared against Cu/low-κ interconnects. The results obtained in this paper are representative of on-die router implementations at 15 nm technology node, which can be used to predict the realistic performance of various NoC topologies.

Original languageEnglish (US)
Title of host publicationProceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017
PublisherIEEE Computer Society
Pages353-359
Number of pages7
ISBN (Electronic)9781509054046
DOIs
StatePublished - May 2 2017
Event18th International Symposium on Quality Electronic Design, ISQED 2017 - Santa Clara, United States
Duration: Mar 14 2017Mar 15 2017

Other

Other18th International Symposium on Quality Electronic Design, ISQED 2017
CountryUnited States
CitySanta Clara
Period3/14/173/15/17

Fingerprint

Nanoribbons
Graphene
Copper
Routers
Topology
Network-on-chip
Clocks
Energy dissipation
Communication

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Pujari, R., & Rakheja, S. (2017). Performance evaluation of copper and graphene nanoribbons in 2-D NoC structures. In Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017 (pp. 353-359). [7918341] IEEE Computer Society. https://doi.org/10.1109/ISQED.2017.7918341

Performance evaluation of copper and graphene nanoribbons in 2-D NoC structures. / Pujari, Ruturaj; Rakheja, Shaloo.

Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017. IEEE Computer Society, 2017. p. 353-359 7918341.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Pujari, R & Rakheja, S 2017, Performance evaluation of copper and graphene nanoribbons in 2-D NoC structures. in Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017., 7918341, IEEE Computer Society, pp. 353-359, 18th International Symposium on Quality Electronic Design, ISQED 2017, Santa Clara, United States, 3/14/17. https://doi.org/10.1109/ISQED.2017.7918341
Pujari R, Rakheja S. Performance evaluation of copper and graphene nanoribbons in 2-D NoC structures. In Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017. IEEE Computer Society. 2017. p. 353-359. 7918341 https://doi.org/10.1109/ISQED.2017.7918341
Pujari, Ruturaj ; Rakheja, Shaloo. / Performance evaluation of copper and graphene nanoribbons in 2-D NoC structures. Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017. IEEE Computer Society, 2017. pp. 353-359
@inproceedings{7603de5dd8e34167beb5b779c52693c1,
title = "Performance evaluation of copper and graphene nanoribbons in 2-D NoC structures",
abstract = "In this paper, performance models of different network-on-chip (NoC) topologies are developed by a) incorporating physical models of the interconnect structures, and b) specifying the microarchitecture of cores and on-chip routers at 15 nm technology node for a clock frequency of 4 GHz. By incorporating device and interconnect models, we implement a cross-layer design and optimization of the performance of NoC architectures. The performance modeling is carried out for mesh, torus, and flattened butterfly (FBFLY) NoC topologies by focusing on global copper (Cu/low-κ) and graphene nanoribbons (GNRs) as the interconnect infrastructure for inter-core communication. The findings show that mesh NoCs incorporated with Cu/low-κ or GNRs have the same latency metrics, while for torus and FBFLY NoCs, the high latency of GNR interconnects is prohibitive. Mesh, torus, and FBFLY topologies with GNRs as inter-core interconnects result in lower interconnect energy dissipation compared to Cu/low-κ interconnects. The worst-case delay for mesh NoCs is equally governed by the on-chip router delay and inter-core interconnects delay but for torus and FBFLY NoCs, delay form inter-core interconnects particularly limits their performance. Therefore, ignoring the interconnect latency in this analysis overestimates the NoC performance significantly. We also determine the optimal network size up to which networks on-chip (NoCs) with GNR interconnects give lower energy-delay product (EDP) when compared against Cu/low-κ interconnects. The results obtained in this paper are representative of on-die router implementations at 15 nm technology node, which can be used to predict the realistic performance of various NoC topologies.",
author = "Ruturaj Pujari and Shaloo Rakheja",
year = "2017",
month = "5",
day = "2",
doi = "10.1109/ISQED.2017.7918341",
language = "English (US)",
pages = "353--359",
booktitle = "Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017",
publisher = "IEEE Computer Society",
address = "United States",

}

TY - GEN

T1 - Performance evaluation of copper and graphene nanoribbons in 2-D NoC structures

AU - Pujari, Ruturaj

AU - Rakheja, Shaloo

PY - 2017/5/2

Y1 - 2017/5/2

N2 - In this paper, performance models of different network-on-chip (NoC) topologies are developed by a) incorporating physical models of the interconnect structures, and b) specifying the microarchitecture of cores and on-chip routers at 15 nm technology node for a clock frequency of 4 GHz. By incorporating device and interconnect models, we implement a cross-layer design and optimization of the performance of NoC architectures. The performance modeling is carried out for mesh, torus, and flattened butterfly (FBFLY) NoC topologies by focusing on global copper (Cu/low-κ) and graphene nanoribbons (GNRs) as the interconnect infrastructure for inter-core communication. The findings show that mesh NoCs incorporated with Cu/low-κ or GNRs have the same latency metrics, while for torus and FBFLY NoCs, the high latency of GNR interconnects is prohibitive. Mesh, torus, and FBFLY topologies with GNRs as inter-core interconnects result in lower interconnect energy dissipation compared to Cu/low-κ interconnects. The worst-case delay for mesh NoCs is equally governed by the on-chip router delay and inter-core interconnects delay but for torus and FBFLY NoCs, delay form inter-core interconnects particularly limits their performance. Therefore, ignoring the interconnect latency in this analysis overestimates the NoC performance significantly. We also determine the optimal network size up to which networks on-chip (NoCs) with GNR interconnects give lower energy-delay product (EDP) when compared against Cu/low-κ interconnects. The results obtained in this paper are representative of on-die router implementations at 15 nm technology node, which can be used to predict the realistic performance of various NoC topologies.

AB - In this paper, performance models of different network-on-chip (NoC) topologies are developed by a) incorporating physical models of the interconnect structures, and b) specifying the microarchitecture of cores and on-chip routers at 15 nm technology node for a clock frequency of 4 GHz. By incorporating device and interconnect models, we implement a cross-layer design and optimization of the performance of NoC architectures. The performance modeling is carried out for mesh, torus, and flattened butterfly (FBFLY) NoC topologies by focusing on global copper (Cu/low-κ) and graphene nanoribbons (GNRs) as the interconnect infrastructure for inter-core communication. The findings show that mesh NoCs incorporated with Cu/low-κ or GNRs have the same latency metrics, while for torus and FBFLY NoCs, the high latency of GNR interconnects is prohibitive. Mesh, torus, and FBFLY topologies with GNRs as inter-core interconnects result in lower interconnect energy dissipation compared to Cu/low-κ interconnects. The worst-case delay for mesh NoCs is equally governed by the on-chip router delay and inter-core interconnects delay but for torus and FBFLY NoCs, delay form inter-core interconnects particularly limits their performance. Therefore, ignoring the interconnect latency in this analysis overestimates the NoC performance significantly. We also determine the optimal network size up to which networks on-chip (NoCs) with GNR interconnects give lower energy-delay product (EDP) when compared against Cu/low-κ interconnects. The results obtained in this paper are representative of on-die router implementations at 15 nm technology node, which can be used to predict the realistic performance of various NoC topologies.

UR - http://www.scopus.com/inward/record.url?scp=85019638290&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85019638290&partnerID=8YFLogxK

U2 - 10.1109/ISQED.2017.7918341

DO - 10.1109/ISQED.2017.7918341

M3 - Conference contribution

AN - SCOPUS:85019638290

SP - 353

EP - 359

BT - Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017

PB - IEEE Computer Society

ER -