Performance, energy-per-bit, and circuit size limits of post-CMOS logic circuits-modeling, analysis and comparison with CMOS logic

Shaloo Rakheja, Azad Naeemi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Original languageEnglish (US)
Title of host publicationIEEE International Interconnect Technology Conference (IITC), Dresden, Germany. May 8-12, 2011
StatePublished - 2011

Cite this

Rakheja, S., & Naeemi, A. (2011). Performance, energy-per-bit, and circuit size limits of post-CMOS logic circuits-modeling, analysis and comparison with CMOS logic. In IEEE International Interconnect Technology Conference (IITC), Dresden, Germany. May 8-12, 2011

Performance, energy-per-bit, and circuit size limits of post-CMOS logic circuits-modeling, analysis and comparison with CMOS logic. / Rakheja, Shaloo; Naeemi, Azad.

IEEE International Interconnect Technology Conference (IITC), Dresden, Germany. May 8-12, 2011. 2011.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rakheja, S & Naeemi, A 2011, Performance, energy-per-bit, and circuit size limits of post-CMOS logic circuits-modeling, analysis and comparison with CMOS logic. in IEEE International Interconnect Technology Conference (IITC), Dresden, Germany. May 8-12, 2011.
Rakheja S, Naeemi A. Performance, energy-per-bit, and circuit size limits of post-CMOS logic circuits-modeling, analysis and comparison with CMOS logic. In IEEE International Interconnect Technology Conference (IITC), Dresden, Germany. May 8-12, 2011. 2011
Rakheja, Shaloo ; Naeemi, Azad. / Performance, energy-per-bit, and circuit size limits of post-CMOS logic circuits-modeling, analysis and comparison with CMOS logic. IEEE International Interconnect Technology Conference (IITC), Dresden, Germany. May 8-12, 2011. 2011.
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